First-in first-out (FIFO) memory with multi-port functionality
AssigneeSTMicroelectronics Pvt. Ltd.
InventorKapil Batra
Life of this patent
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Abstract
A memory may require buffering mechanism in which data can be written and read at the same time. This requires a multi-port FIFO memory, which has multiple ports, thus providing simultaneous read & write operations. Multi-port memories have a large penalty on area. Hence, a technique is proposed for avoiding use of multi-port memories for designs, which requires sequential read and write operations. In this technique multiple single-port memories are used to form a multi-port memory. This memory requires additional control logic but consumes significantly lower silicon area.
Claims20
A first-in first-out (FIFO) memory providing multi-port functionality, the FIFO memory comprising:
- a plurality of said single-port memory structures;
- an indexing block to store information corresponding to incoming data for each data write operation in the single-port memory structure;
- and
- an access controller to control operations in the single-port memory structures based on the contents of the indexing block.
A method of operating a plurality of single port memory structures as a multi-port memory for sequential memory operations, the method comprising:
- maintaining a unique identifier corresponding to each said single port memory structure;
- performing a “read operation active” check to find which of the single port memory structures is free for a data write operation;
- and
- storing the unique identifier corresponding to the single port memory in which the data write operation is done in an indexing block;
- and
- performing data read operation based on the contents of said indexing block to ascertain the single port memory which has to be read.
A first-in first-out (FIFO) memory structure providing multi-port functionality, the FIFO memory comprising:
- a plurality of single-port memory structures;
- an access controller to maintain the pointer information for read and write operation in the plurality of single-port memory structures;
- and
- an indexing block to store memory identifier corresponding to each of the single-port memory structures.
Dependencies are inferred from the claim text.