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US 2007/0183239 A1Published application
Semiconductor memory device including plurality of memory mats
AssigneeRenesas Technology Corp.
InventorKoji Kishi
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a plurality of memory mats each including a memory cell storing data, a sense latch portion performing detection of data stored by the memory cell, and a buffer circuit externally outputting read data detected by the sense latch portion. The sense latch portion and the buffer circuit are shared between a plurality of memory mats and are arranged between a plurality of memory mats.
Claims7
A semiconductor memory device comprising:
- a plurality of memory mats each including a memory cell storing data;
- a sense amplifier performing detection of data stored by said each memory cell;
- and
- a buffer circuit externally outputting read data detected by said sense amplifier, wherein
- said sense amplifier and said buffer circuit are shared between said plurality of memory mats and are arranged between said plurality of memory mats.
2 more elements
A semiconductor memory device comprising:
- a first memory mat and a second memory mat each including a memory cell storing data;
- at least one first current line arranged for each of said memory mats and connected to one conductive electrode of said memory cell;
- a sense latch shared between said memory mats, storing electric charges corresponding to write data for said memory cell in said first current line and detecting data stored by said memory cell based on a voltage value or a current value of said first current line;
- at least one second current line arranged for each of said memory mats;
- a plurality of first transistors arranged corresponding to said first current line for switching between connection and disconnection between said first current line and said second current line;
- a plurality of second transistors arranged corresponding to said first current line for switching between connection and disconnection between said first current line and said sense latch;
- at least one third current line arranged for each of said memory mats;
- and
- a plurality of third transistors arranged corresponding to said first current line for switching between connection and disconnection between the other conductive electrode of said memory cell and said third current line.
6 more elements
Dependencies are inferred from the claim text.