Semiconductor memory apparatus
AssigneeHynix Semiconductor Inc.
InventorMun Phil Park
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus includes a main bank configured to combine a first sub bank and a second sub bank. A center bitline sense amplifier array is arranged in a region where the first sub bank meets the second sub bank. A first precharge section is arranged above the first sub bank and a second precharge section is arranged below the second sub bank. The first precharge section precharges local input/output lines of the first sub bank and the second sub bank and the second precharge section precharges the local input/output lines.
Claims13
A semiconductor memory apparatus comprising:
- a main bank configured to combine a first sub bank and a second sub bank;
- a center bitline sense amplifier array arranged in a region where the first sub bank meets the second sub bank;
- a first precharge section arranged above the first sub bank, wherein the first precharge section is configured to precharge local input/output lines of the first sub bank and the second sub bank;
- and
- a second precharge section arranged in the center bitline sense amplifier array, wherein the second precharge section is configured to precharge the local input/output lines.
A semiconductor memory apparatus comprising:
- a main bank configured to combine a first sub bank and a second sub bank;
- a center bitline sense amplifier array arranged in a region where the first sub bank meets the second sub bank;
- a first precharge section arranged below the second sub bank, wherein the first precharge section is configured to precharge local input/output lines of the first sub bank and the second sub bank;
- and
- a second precharge section arranged in the center bitline sense amplifier array, wherein the second precharge section is configured to precharge the local input/output lines.
Dependencies are inferred from the claim text.