Semiconductor memory device having reduced voltage coupling between bit lines

A semiconductor memory device, comprising:

• an array of memory cells, each memory cell being connected to a word line pair and between a pair of bit lines;
• and
• a first precharging and equalizing circuit connected to a first bit line pair connected to a first memory cell connected to a first word line;
• and
• a second precharging and equalizing circuit connected to a second bit line pair connected to a second memory cell connected to the first word line, wherein the first memory cell is adjacent to the second memory cell.

A method for performing a write operation in a semiconductor memory device comprising a first memory cell connected to a first word line and between a first pair of bit lines and a second memory cell connected to the first word line and between a second pair of bit lines, the method comprising:

• applying an equalization release signal to a first precharging and equalizing circuit connected to the first bit line pair;
• applying an equalization release signal to a second precharging and equalizing circuit connected to the second bit line pair when the first word line is activated after a write driver is enabled;
• and
• writing write data to the first memory cell before the second precharging and equalizing circuit connected to the second bit line pair is disabled.

A method for performing write operation in a semiconductor memory device comprising an array of memory cells, each memory cell having three-dimensional stack and being connected to a word line and between a pair of bit lines, the method comprising:

• applying an equalization release signal to a first precharging and equalizing circuit connected to a first pair of bit lines;
• applying equalization release signals to a second precharging and equalizing circuit connected to a second pair of bit lines and to a third precharging and equalizing circuit connected to a third pair of bit lines when a word line is activated after a write driver is enabled;
• and
• writing write data to a first memory cell connected to the word line and between the first pair of bit lines immediately after the second and third precharging and equalizing circuits are disabled.