Semiconductor memory device
AssigneeElpida Memory, Inc.
InventorKazuyuki Okada
Life of this patent
Estimating the term…
Abstract
In a semiconductor memory device employing shared type sense amplifiers, entry is made to the test mode, and transfer gates, pre-charge circuits, and sense amplifiers used in the shared type sense amplifiers are controlled individually. An object bit line is placed in the high impedance state. The opposing sense amplifier is left active to place an adjacent bit line in the low impedance state. If there is a bit-line to bit-line short, data on the object bit line in the high impedance state is inverted from the adjacent bit line in the low impedance state. The bit-line to bit-line short can be detected by reading the inverted data.
Claims17
A semiconductor memory device employing shared type sense amplifiers, the semiconductor memory device having a test mode for detecting a bit-line to bit-line short by placing in the high impedance state a first bit line connected to a first sense amplifier arranged on a first side of a selected memory array, while placing in the low impedance state a second bit line connected to a second sense amplifier arranged on a second side of the selected memory array opposing the first side.
A semiconductor memory device comprising a first sense amplifier shared by a first memory array and a second memory array, a second sense amplifier shared by a first memory array and a third memory array, wherein:
- the first semiconductor memory array comprises a first complementary bit line pair connected to the first sense amplifier via a first switch, a second complementary bit line pair connected to the second sense amplifier via a second switch, a bit line of the second complementary bit line pair being arranged adjacent to a bit line of the first complementary bit line pair, and
- control circuit for controlling the first switch and the second switch, and wherein:
- a bit line to bit line short is detected by putting the first bit line pair into a high impedance state and the second bit line pair into a low impedance state in response to a test mode set command.
A method of identifying short in lines in memory arrays of a semiconductor memory device comprising a first sense amplifier shared by a first memory array and a second memory array, a second sense amplifier shared by a first memory array and a third memory array, the first semiconductor memory array comprises a first complementary bit line pair connected to the first sense amplifier via a first switch, a second complementary bit line pair connected to the second sense amplifier via a second switch, a bit line of the second complementary bit line pair being arranged adjacent to a bit line of the first complementary bit line pair,
- the method comprising steps of:
- writing cell data into memory cells so that the first and second bit lines assume opposite logic levels,
- putting the first bit line pair into a high impedance state and the second bit line pair into a low impedance state in response to a test mode set command, and
- reading cell data from the memory cells to see if there is an inversion of a written logic level.
Dependencies are inferred from the claim text.