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US 2007/0183227 A1Published application
Delay line circuit
AssigneeMicron Technology, Inc.
InventorsKang Kim, Jongtae Kwak
Life of this patent
Estimating the term…
Abstract
Methods, circuits, devices, and systems are provided, including a delay line for a delay-locked loop. One method includes providing a reference clock to a first delay unit in a delay line. The delay line includes a number of delay units coupled together. Even delay units, among the delay units, are coupled to an even clock line to generate a first intermediate clock. Odd delay units are coupled to an odd clock line to generate a second intermediate clock. The even and odd delay units are configured to in a manner intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units.
Claims35
A method of producing a clock signal, comprising:
- providing a reference clock to a first delay unit in a delay line, wherein the delay line includes a number of delay units coupled together;
- coupling even delay units, among the delay units, to an even clock line to generate a first intermediate clock;
- and
- coupling odd delay units, among the delay units, to an odd clock line to generate a second intermediate clock in a configuration intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units.
1 more element
A method of producing a clock signal, comprising:
- providing a reference clock to a first delay unit in a delay line, wherein the delay line includes a number of delay units coupled together;
- coupling even delay units through all like-type gates to an even clock line to generate a first intermediate clock;
- and
- coupling odd delay units through all like-type gates to an odd clock line to generate a second intermediate clock in a configuration intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units.
1 more element
A method for clock synchronization, comprising:
- coupling an even clock line signal through gates in even delay units among a number of delay units to generate a first intermediate clock from a reference clock signal;
- and
- coupling an odd clock line signal through gates in odd delay units among the number of delay units to generate a second intermediate clock from the reference clock signal in a configuration intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units.
A delay line circuit, comprising:
- a number of delay units coupled together;
- a reference clock input is coupled to a first delay unit in the delay line;
- a number of even delay units, among the delay units, coupled to an even clock line to generate a first intermediate clock;
- and
- a number of odd delay units, among the delay units, coupled to an odd clock line to generate a second intermediate clock in a configuration intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units.
2 more elements
A delay line circuit, comprising:
- a number of delay units coupled together;
- a reference clock input to a first delay unit in the delay line circuit;
- a number of even delay units, among the delay units, coupled together through all like-type gates to form an even clock line and to generate a first intermediate clock;
- a number of odd delay units, among the delay units, coupled together through all like-type gates to form an odd clock line and to generate a second intermediate clock in a configuration intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units;
- and
- a phase mixer coupled to the even clock line and the odd clock line.
3 more elements
A synchronization circuit, comprising:
- a course delay line having an even clock line and an odd clock line, wherein even delay units are coupled to the even clock line and odd delay units are coupled to the odd clock line in a configuration intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units and to maintain a two gate delay difference between the even and the odd clock lines;
- and
- a phase mixer coupled to the even and the odd clock lines.
A method of forming a delay line, comprising:
- forming a number of delay units with each delay unit having a number of gates coupled together;
- forming a first delay unit in the delay line with a reference clock input;
- forming an even clock line from coupling even delay units, among the delay units, to generate a first intermediate clock;
- and
- forming an odd clock line from coupling odd delay units, among the delay units, to generate a second intermediate clock in a configuration intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units.
2 more elements
A memory device, comprising:
- a memory array;
- a row decoder coupled to the memory array;
- a column decoder coupled to the memory array;
- and
- an input/output (I/O) circuit coupled to the column decoder, wherein the I/O circuit includes a delay line, the delay line including:
- a number of delay units coupled together;
- a reference clock input to a first delay unit in the delay line;
- a number of even delay units, among the delay units, coupled to an even clock line to generate a first intermediate clock;
- and
- a number of odd delay units, among the delay units, coupled to an odd clock line to generate a second intermediate clock in a configuration intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units.
7 more elements
A memory device, comprising:
- a memory array;
- a row decoder coupled to the memory array;
- a column decoder coupled to the memory array;
- and
- an input/output (I/O) circuit coupled to the column decoder, wherein the I/O circuit includes a synchronization circuit, the synchronization circuit including:
- a course delay line having an even clock line and an odd clock line, wherein even delay units are coupled to the even clock line and odd delay units are coupled to the odd clock line in a configuration intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units and to maintain a two gate delay difference between the even and the odd clock lines;
- and
- a phase mixer coupled to the even and the odd clock lines.
5 more elements
A processor based system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, wherein the memory device includes:
- a memory array;
- a row decoder coupled to the memory array;
- a column decoder coupled to the memory array;
- and
- an input/output (I/O) circuit coupled to the column decoder, wherein the I/O circuit includes a delay line circuit, the delay line circuit including:
- a number of delay units coupled together;
- a reference clock input to a first delay unit in the delay line circuit;
- a number of even delay units, among the delay units, coupled together to form an even clock line and to generate a first intermediate clock;
- a number of odd delay units, among the delay units, coupled together to form an odd clock line and to generate a second intermediate clock in a configuration intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units;
- and
- a phase mixer coupled to the even clock line and the odd clock line.
13 more elements
Dependencies are inferred from the claim text.