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US 2007/0183223 A1Published application
Memory block erasing in a flash memory device
AssigneeMicron Technology, Inc.
InventorSeiichi Aritome
Life of this patent
Estimating the term…
Abstract
The erase and verify method performs an erase operation and an erase verify read operation. If the erase verify read operation fails because unerased memory cells have been found, a normal memory read operation is performed in order to determine which memory cells are still programmed. A selective erase operation is then performed on the memory cells such that only the rows that comprise unerased memory cells undergo additional erase operations.
Claims17
A memory system comprising:
- a controller that generates memory signals;
- and
- a non-volatile memory device, coupled to the controller, that operates in response to the memory signals, the device comprising:
- an array of memory cells arranged in a plurality of memory blocks, each memory block having a plurality of memory cells that are arranged in rows and columns such that the rows are coupled to word lines and the columns are coupled to bit lines;
- and
- a control circuit that is adapted to execute an erase operation on a first memory block of the plurality of memory blocks, the operation comprising performing an erase verify read operation on the first memory block, performing a selective memory read operation of the memory block to determine which of the plurality of memory cells is unerased if one or more of the plurality of memory cells is unerased, and performing a selective erase operation on the unerased memory cells.
3 more elements
A memory system comprising:
- a processor capable of interacting with a memory device;
- and
- a non-volatile Flash memory device interacting with the processor, the Flash memory device comprising:
- an array of Flash memory cells, arranged in a plurality of blocks, each memory block having a plurality of memory cells that are arranged in rows and columns such that rows are coupled to word lines and the columns are coupled to bit lines, each column having a source select transistor and a drain select transistor located at opposite ends of each column;
- and
- a control circuit that is adapted to execute an erase operation on a first memory block of the plurality of memory blocks, the operation comprising performing an erase verify read operation on the first memory block, performing a selective memory read operation of the memory block to determine which of the plurality of memory cells is unerased if one or more of the plurality of memory cells is unerased, and performing a selective erase operation on the unerased memory cells.
3 more elements
The memory system of claim 10 wherein the control circuit is adapted such that a erase verify operation comprises:
- biasing each unselected wordline at ground potential;
- biasing any selected bit lines at Vcc;
- biasing any unselected bit lines at ground potential;
- and
- biasing the drain and source select transistors at a Vpass potential. The memory system of claim 17 wherein the Vpass potential is substantially equal to 4.5V. The memory system of claim 10 wherein the control circuit is further comprised of current sense amplifiers to measure current flowing in columns of the memory array. The memory system of claim 19 wherein the control circuit is further adapted to compare current flowing in memory array columns to a reference current as part of an erase verify read operation.
2 more elements
Dependencies are inferred from the claim text.