US 2007/0183214 A1 · Semiconductor device undergoing defect detection test

Abstract

A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.

Claims10

Dependent claims

A semiconductor device having a first operation mode and a second operation mode in which a positive voltage and a ground voltage are externally supplied and the positive voltage in said second operation mode is higher than the positive voltage in said first operation mode, comprising:

a memory portion including a memory cell storing data;
and
a power supply circuit portion supplying a first voltage and a second voltage to said memory portion, wherein
said memory portion writes data to or reads data from said memory cell based on said first voltage and said second voltage, and
said power supply circuit portion includes:
a boosted voltage generation circuit generating, based on said externally supplied positive voltage and ground voltage, a boosted voltage of said positive voltage;
a negative voltage generation circuit generating a negative voltage based on said externally supplied positive voltage and ground voltage;
and
a switch circuit supplying, in said first operation mode, said boosted voltage as said first voltage and said negative voltage as said second voltage to said memory portion, and providing, in said second operation mode, a smaller voltage difference between said first voltage and said second voltage relative to said first operation mode.

6 more elements

a memory portion including a memory cell storing data;
and
a power supply circuit portion supplying a voltage to said memory portion, wherein
said memory cell stores electric charge according to a logic level of data and includes a first memory cell capacitor and a second memory cell capacitor having a common electrode, and
said power supply circuit portion includes:
a cell plate voltage generation circuit generating a cell plate voltage based on said externally supplied positive voltage and ground voltage;
and
a cell plate voltage switch circuit supplying said cell plate voltage to the common electrode of said first and second memory cell capacitors in said first operation mode and supplying a voltage higher or lower than said cell plate voltage to said common electrode in said second operation mode.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor device undergoing defect detection test

Life of this patent

Semiconductor device undergoing defect detection test

Life of this patent

Abstract

Claims10