3-Level non-volatile semiconductor memory devices and related methods

A non-volatile semiconductor memory device, comprising:

• a memory array including first and second memory cells and first and second word lines respectively coupled to the first and second memory cells;
• a page buffer configured to map data of a set of first, second, and third bits to threshold voltage levels of the first and second memory cells;
• and
• a row decoder configured to control the first and second word lines respectively applied to the first and second memory cells, to first and second reference voltages, the first and second reference voltages having different voltage levels.

A method of driving a non-volatile semiconductor memory device wherein data of a set of first, second, and third bits are mapped to a pair of first and second memory cells, the method comprising:

• A) resetting lower latch data and upper latch data;
• B) flipping the lower latch data using a threshold voltage of the first memory cell, which uses a first reference voltage as a reference, and flipping the upper latch data using a threshold voltage of the second memory cell, which uses a second reference voltage as a reference, the threshold voltages of the first and second memory cells being classified into first, second, and third threshold voltage groups based on the first reference voltage and the second reference voltage, wherein the second reference voltage is higher than the first reference voltage;
• and
• C) flipping the lower latch data using the previously flipped upper latch data.