Controlling a nonvolatile storage device

A semiconductor device comprising:a memory cell including first and second diffusion layers and an insulating trapping layer located close to the first and second diffusion layers and having first and second trapping regions for trapping charges therein;

• a first dynamic reference cell having an equivalent structure to the memory cell wherein the first trapping region of the first dynamic reference cell is set in a charge accumulated state;
• a second dynamic reference cell having an equivalent structure to the memory cell wherein the first trapping region of the second dynamic reference cell is set in a charge depleted state;
• and
• an initializing circuit for initializing the first and second dynamic reference cells when a data storage operation stores one-bit data in accordance with the presence or absence of charges in the first trapping region of the memory cell, the initializing circuit comprising:
• a presetting circuit for presetting the second trapping regions of the memory cell and the first and second dynamic reference cells into the charge accumulated state;
• and
• a setting circuit for setting the first trapping region of the first dynamic reference cell into the charge accumulated state in accordance with the data storage operation of the memory cell after the presetting circuit has preset the second trapping regions of the memory cell and the first and second dynamic reference cells into the charge accumulated state.

In a nonvolatile storage device, comprising a memory cell including first and second diffusion layers and an insulating trapping layer that is located close to the first and second diffusion layers and has first and second trapping regions for trapping charges therein, a method comprising the steps of:

• prior to a data rewriting operation in the case where one-bit data is stored according to the presence or absence of charges in the first trapping region, checking a trapping state of charges with respect to the first trapping region of the memory cell;
• performing a charge accumulating operation when it is confirmed that the first trapping region is in a charge depleted state;
• and
• setting the first trapping regions of all the memory cells into the charge accumulated state and then performing a charge depleting operation with respect to the first and second trapping regions.

A wireless communications device, comprising:

• a flash memory comprising:
• a memory cell including first and second diffusion layers and an insulating trapping layer located close to the first and second diffusion layers and having first and second trapping regions for trapping charges therein;
• a first dynamic reference cell having an equivalent structure to the memory cell wherein the first trapping region of the first dynamic reference cell is set in a charge accumulated state;
• a second dynamic reference cell having an equivalent structure to the memory cell wherein the first trapping region of the second dynamic reference cell is set in a charge depleted state;
• and
• a circuit for initializing the first and second dynamic reference cells when a data storage operation stores one-bit data in accordance with the presence or absence of charges in the first trapping region of the memory cell, the circuit comprising:
• a presetting circuit for presetting the second trapping regions of the memory cell, first and second dynamic reference cells into the charge accumulated state;
• and
• a setting circuit for setting the first trapping region of the first dynamic reference cell into the charge accumulated state in accordance with the data storage operation of the memory cell after the presetting circuit presets the second trapping regions of the memory cell, first and second dynamic reference cells into the charge accumulated state;
• a communications component;
• a transmitter;
• a receiver;
• and
• an antenna connected to the transmitter circuit and the receiver circuit.

A computing device comprising:

• a processor;
• an input component;
• an output component;
• a memory comprising:
• a volatile memory;
• and
• a flash memory comprising:
• a memory cell including first and second diffusion layers and an insulating trapping layer located close to the first and second diffusion layers and having first and second trapping regions for trapping charges therein;
• a first dynamic reference cell having an equivalent structure to the memory cell wherein the first trapping region of the first dynamic reference cell is set in a charge accumulated state;
• a second dynamic reference cell having an equivalent structure to the memory cell wherein the first trapping region of the second dynamic reference cell is set in a charge depleted state;
• and
• a circuit for initializing the first and second dynamic reference cells when a data storage operation stores one-bit data in accordance with the presence or absence of charges in the first trapping region of the memory cell, the circuit comprising:
• a presetting circuit for presetting the second trapping regions of the memory cell, first and second dynamic reference cells into the charge accumulated state;
• and
• a setting circuit for setting the first trapping region of the first dynamic reference cell into the charge accumulated state in accordance with the data storage operation of the memory cell after the presetting circuit presets the second trapping regions of the memory cell, first and second dynamic reference cells into the charge accumulated state.

A portable media player comprising:

• a processor;
• a cache;
• a user input component;
• a coder-decoder component;
• and
• a memory comprising:
• a flash memory comprising:
• a memory cell including first and second diffusion layers and an insulating trapping layer located close to the first and second diffusion layers and having first and second trapping regions for trapping charges therein;
• a first dynamic reference cell having an equivalent structure to the memory cell wherein the first trapping region of the first dynamic reference cell is set in a charge accumulated state;
• a second dynamic reference cell having an equivalent structure to the memory cell wherein the first trapping region of the second dynamic reference cell is set in a charge depleted state;
• and
• a circuit for initializing the first and second dynamic reference cells when a data storage operation stores one-bit data in accordance with the presence or absence of charges in the first trapping region of the memory cell, the circuit comprising:
• a presetting circuit for presetting the second trapping regions of the memory cell, first and second dynamic reference cells into the charge accumulated state;
• and
• a setting circuit for setting the first trapping region of the first dynamic reference cell into the charge accumulated state in accordance with the data storage operation of the memory cell after the presetting circuit presets the second trapping regions of the memory cell, first and second dynamic reference cells into the charge accumulated state.