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US 2007/0183181 A1Published application
Electrically programmable fuse bit
AssigneeKilopass Technology, Inc.
InventorsJack Peng, David Fong, Glen Rosendale
Life of this patent
Estimating the term…
Abstract
One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.
Claims41
A nonvolatile programmable read only memory cell with continuously available data content without decoding or addressing, the memory cell comprising:
- a select transistor having a source, a drain, and a gate, wherein the source or the drain of the select transistor is connected to a first voltage and the other of the source and the drain forms a first connection point;
- and
- a fuse transistor having a source, a drain, and a gate, wherein:
- the source, the drain, or the source and the drain of the fuse transistor forms a second connection point, wherein the second connection point is an output port of the memory cell;
- the first and the second connection points are electrically connected;
- and
- data of certain logic level is programmed in the cell through permanently altering at least one physical characteristic of the fuse transistor by turning on the select transistor and applying a controlled high voltage to the gate of the fuse transistor for a predetermined period of time.
4 more elements
A programmable read only memory circuit configured to be a part of a multi-bit memory block, the memory circuit comprising:
- a single-bit core memory cell comprising at least a select device, a high-voltage protection device, and a fuse device in series, wherein data is programmed in the cell through permanently altering at least one physical characteristic of the fuse device by turning on the select device and applying a controlled high voltage to the gate of the fuse device for a predetermined period of time;
- a single-bit latch for latching an output of the single-bit core memory cell or an externally provided data bit;
- a set and a reset input line for controlling the single-bit latch content;
- a block-select input line for selecting a memory block among a plurality of memory blocks;
- multiple address input lines for selecting a memory circuit among a plurality of memory circuits of a memory block;
- and
- a programming input line for enabling programming of memory circuits of a selected memory block.
4 more elements
A programmable read only single-bit memory cell using two differentially programmable fuses, the memory cell comprising:
- a set-reset latch with a first and a second latched output, wherein the first latched output is a complement of the second latched output, and wherein one of the latched outputs indicates a stored data value in the memory cell and the other latched output indicates the complement of the stored data value in the memory cell;
- and
- two differentially programmed core memory cells, each comprising:
- a select transistor having a source, a drain, and a gate, wherein the source or the drain of one of the two select transistors is connected to the first or the second output of the set-reset latch and the source or the drain of the other select transistor is connected to the other of the first and the second output of the set-reset latch;
- and
- a fuse transistor having a source, a drain, and a gate, wherein:
- the source, the drain, or the source and drain of each of the two fuse transistors are connected to the other source or drain of the two select transistors;
- and
- data is programmed in the memory cell by permanently altering at least one physical characteristic of one of the two fuse transistors, in a differential manner, through connecting a first and a second controlled voltage to the gates of the select and the fuse transistors, respectively, for predetermined periods of time while having appropriate logic values at the set and the reset inputs of the set-reset latch.
6 more elements
A single-bit nonvolatile programmable memory cell using two differentially programmed fuses, the memory cell comprising:
- a set-reset latch with a first and a second latched output, wherein the first output is a complement of the second output, and wherein one of the latched outputs indicates a stored logic value in the memory cell and the other latched output indicates the complement of the stored logic value in the memory cell;
- and
- two differentially programmable transistors, each comprising a source, a drain, and a gate, wherein:
- the source, the drain, or the source and the drain of the two programmable transistors are connected to a controllable voltage, and wherein the gate of one of the two programmable transistors is connected to the first output of the set-reset latch and the gate of the other programmable transistor is connected to the second output of the set-reset latch;
- and
- data is programmed in the memory cell by permanently altering a characteristic of one of the differentially programmed transistors via keeping the controllable voltage at a predetermined voltage for a predetermined period of time while having appropriate logic values at the set and the reset inputs of the set-reset latch.
3 more elements
A data bit storage method comprising:
- connecting each output of two differentially programmable core memory cells to one of two complementary outputs of a set-reset latch, wherein each core memory cell comprises:
- a select transistor having a source, a drain, and a gate, wherein the source or the drain of one of the two select transistors is connected to the first or the second output of the set-reset latch and the source or the drain of the other select transistor is connected to the other of the first and the second output of the set-reset latch;
- and
- a fuse transistor having a source, a drain, and a gate, wherein the source, the drain, or the source and drain of each of the two fuse transistors are connected to the other source or drain of the two select transistors;
- and
- storing a data value by permanently altering a physical characteristic of one of the two fuse transistors, in a differential manner, through connecting a first and a second controlled voltage to the gates of the select and the fuse transistors, respectively, for predetermined periods of time while having appropriate logic values at the set and the reset inputs of the set-reset latch, wherein one of the latched outputs indicates the stored data value and the other latched output indicates the complement of the stored data value.
3 more elements
A data storage method comprising:
- connecting each output of two differentially programmable core memory cells to one of two complementary outputs of a set-reset latch, wherein each core memory cell comprises two differentially programmable transistors, each further comprising a source, a drain, and a gate, and wherein the source, the drain, or the source and the drain of the two programmable transistors are connected to a controllable voltage, and wherein the gate of one of the two programmable transistors is connected to the first output of the set-reset latch and the gate of the other programmable transistor is connected to the second output of the set-reset latch;
- and
- storing data by permanently altering a characteristic of one of the differentially programmed transistors via keeping the controllable voltage at a predetermined voltage for a predetermined period of time while having appropriate logic values at the set and the reset inputs of the set-reset latch, wherein one of the latched outputs indicates a stored data and the other latched output indicates the complement of the stored data.
A nonvolatile memory cell comprising a select transistor coupled in series with a data storage element, wherein:
- the data storage element comprises a conductive structure the conductivity of which is controllably altered;
- the select transistor has a gate that is controllable to address the memory cell for programming;
- and
- the storage element is read at all times by sensing a current through the storage element at the coupling point of the two transistors.
1 more element
A one-time programmable memory circuit comprising:
- a single-bit core memory means for storing a single data bit, wherein the data bit is programmed in the memory means by permanently altering capacitance of a fuse device;
- a single-bit latch means for latching an output of the single-bit core memory means or latching an externally provided data bit, wherein:
- the single-bit latch is implemented by two cross-coupled NAND-gates;
- the fuse data is connected to the single-bit latch through at least one transistor and a signal at the transistor gate controls the fuse data passage;
- and
- an input of the single-bit latch is connected to ground through at least one transistor, a gate of which is controlled by the fuse data and is also connected to ground by at least one leakage control transistor;
- a set and a reset means for controlling the single-bit latch content;
- a block-select input means for selecting a block of multiple memory circuits among a plurality of memory circuit blocks;
- multiple address input means for selecting a memory circuit among multiple memory circuits of a memory circuit block;
- and
- a programming input means for enabling programming of memory circuits of a selected memory circuit block.
8 more elements
Dependencies are inferred from the claim text.