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US 2007/0183006 A1Published application
Analog-to-digital conversion in CMOS image sensor
AssigneeSamsung Electronics Co., Ltd.
InventorKwang-Hyun Lee
Life of this patent
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Abstract
An analog-to-digital converter in an image sensor is implemented with a plurality of comparator units. Each comparator unit has a respective capacitor array and respective switches integrated therein. Such capacitors and switches across the comparator units are operated for generating ramp voltages for such comparator units for performing analog-to-digital conversion with correlated double sampling. Thus, circuit area and power consumption of the CMOS image sensor may be minimized.
Claims20
An analog-to-digital converter in an image sensor, comprising:
- a plurality of comparator units each including:
- a respective comparator;
- a first respective capacitor coupled between a first node and a respective third node;
- a second respective capacitor coupled between a second node and a respective fourth node;
- a third respective capacitor coupled between the first node and a first input of the respective comparator;
- a fourth respective capacitor coupled between the second node and a second input of the respective comparator;
- and
- respective switches;
- and
- a controller for controlling the respective switches to couple a subset of the first respective capacitors of the plurality of comparator units between the first node and a first reference voltage, and to couple another subset of the first respective capacitors between the first node and a second reference voltage, for generating a first ramp voltage at the first node,
- and wherein the controller controls the respective switches to couple a subset of the second respective capacitors of the plurality of comparator units between the second node and the first reference voltage, and to couple another subset of the second respective capacitors between the second node and the second reference voltage, for generating a second ramp voltage at the second node.
8 more elements
An image sensor comprising:
- a pixel array;
- a row driver for controlling the pixel array to generate a respective pixel signal and a respective reset signal for each of a plurality of pixels;
- a plurality of comparator units each including for a corresponding one of the pixels:
- a respective comparator;
- a first respective capacitor coupled between a first node and a respective third node;
- a second respective capacitor coupled between a second node and a respective fourth node;
- a third respective capacitor coupled between the first node and a first input of the respective comparator;
- a fourth respective capacitor coupled between the second node and a second input of the respective comparator;
- and
- respective switches;
- and
- a controller for controlling the respective switches to couple a subset of the first respective capacitors of the plurality of comparator units between the first node and a first reference voltage, and to couple another subset of the first respective capacitors between the first node and a second reference voltage, for generating a first ramp voltage at the first node,
- and wherein the controller controls the respective switches to couple a subset of the second respective capacitors of the plurality of comparator units between the second node and the first reference voltage, and to couple another subset of the second respective capacitors between the second node and the second reference voltage, for generating a second ramp voltage at the second node.
10 more elements
A method of performing analog-to-digital conversion within an image sensor comprising:
- coupling a pixel signal to a first input of a respective comparator and coupling a reset signal to a second input of the respective comparator within a respective comparator unit for a corresponding pixel of the image sensor;
- wherein the respective comparator unit includes respective switches, a first respective capacitor coupled between a first node and a respective third node, a second respective capacitor coupled between a second node and a respective fourth node, a third respective capacitor coupled between the first node and the first input of the respective comparator, and a fourth respective capacitor coupled between the second node and the second input of the respective comparator;
- and
- controlling the respective switches to couple a subset of the first respective capacitors of a plurality of comparator units between the first node and a first reference voltage, and to couple another subset of the first respective capacitors between the first node and a second reference voltage, to generate a first ramp voltage at the first node;
- and
- controlling the respective switches to couple a subset of the second respective capacitors of the plurality of comparator units between the second node and the first reference voltage, and to couple another subset of the second respective capacitors between the second node and the second reference voltage, to generate a second ramp voltage at the second node.
3 more elements
Dependencies are inferred from the claim text.