System and Method for Vector Computations in Arithmetic Logic Units (ALUS)

A graphics processing apparatus comprising:

• a register file;
• logic for managing a plurality of threads;
• a plurality of arithmetic logic units (ALUs);
• and
• data configuring logic capable of selectively configuring consecutive data in the register file associated with a given processing thread to be successively delivered to a single one of the ALUs in response to a first processing mode, said data configuring logic capable of selectively configuring consecutive data in the register file associated with a given processing thread to be successively delivered to different ones of the ALUs in response to a second processing mode.

A method for processing instructions and data comprising:

• receiving instructions and associated data from a register file;
• determining which one of two modes is active for the received instructions and associated data;
• delivering the instructions and data directly to a plurality of arithmetic logic units (ALUs) for processing, without reorganizing, when a first mode is active;
• and
• reorganizing the instructions and data, and then delivering the instructions and data to the plurality of ALUs for processing, when a second mode is active.

A method for processing operations in a plurality of arithmetic logic units (ALUs) comprising:

• retrieving an instruction and associated data from a register file;
• determine a mode of operation;
• delivering the retrieved instruction and associated data directly to the plurality of ALUs if the mode is determined to be a horizontal mode;
• and
• reformatting the retrieved instruction and associated data such that items originally formatted for delivery to adjacent ALUs are reformatted for delivery into a single ALU, and thereafter delivering the reformatted instruction and associated data to the plurality of ALUs.