Electrical circuit arrangement for a display device
AssigneeKoninklijke Philips Electronics N.V.
InventorAdrianus Sempel
Life of this patent
Estimating the term…
Abstract
The electrical circuit arrangement (A) for a display device (6) comprises an input terminal (11;13) a first memory element (M1); a driver element (D) coupled to the first memory element (M1); and a calibration circuit (S) coupled between the driver element (D) and the input terminal (11; 13). Information about first signal (Iprog;Idat) received via the input terminal (11; 13) is stored in the first memory element (M1). The driver element provides a second signal (Ilight; Iprog) via an output terminal (15; 11) in accordance with the information as stored in the first memory element (M1). The calibration circuit (S) matches a potential difference between the driver element (D) and the input terminal (11; 13) during a calibration phase prior to receiving the first signal (Iprog; Idat).
Claims15
1-14. (canceled)
Electrical circuit arrangement (A) for a display device (6), the electrical circuit arrangement (A) comprising an input terminal (11;13) for receiving a first signal (Iprog;Idat);
- a first memory element (M1) for storing information about the first signal (Iprog;Idat);
- a driver element (D) coupled to the first memory element (M1) for outputting a second signal (Ilight;Iprog) via an output terminal (15;11) in accordance with the information about the first signal;
- a calibration circuit (S) coupled between the driver element (D) and the input terminal (11;13) for matching a potential difference between the driver element (D) and the input terminal (11;13) during a calibration phase prior to receiving the first signal (Iprog;Idat), the matching being such that there is no voltage change required at the input terminal (11;13) during a subsequent programming phase if during this programming phase the second signal has to be programmed to the same value as during the previous programming phase.
Method for addressing a display pixel (3) of a display device (6) comprising an input terminal (11), a first memory element (M1;
- C), a second memory element (M2;
- Ccal), a driver transistor (T2) coupled to an output terminal (15), and a calibration circuit (S) coupled between the driver transistor (T2) and the input terminal (11), the method comprising the steps of:
- storing information about a first signal (Iprog) in said first memory element (C);
- generating a second signal (Ilight) from said driver transistor (T2) in accordance with the information about the first signal (Iprog);
- enabling the calibration circuit (S) to match a potential difference between the driver transistor (T2) and the input terminal (11) during a calibration phase prior to receiving the first signal (Iprog), the matching being such that there is no voltage change required at the input terminal (11) during a subsequent programming phase if during this programming phase the second signal has to be programmed to the same value as during the previous programming phase.
Dependencies are inferred from the claim text.