Circuits and methods for phase locked loop lock window detection

Abstract

Circuits and methods for detecting the lock status of a phase locked loop (PLL). The circuit generally comprises (a) a controller configured to produce a control signal in response to a reference clock signal, (b) a counter configured to count pulses of an output signal of the PLL (or a periodic derivative of the output signal) in response to the control signal, and (c) a decoder configured to (i) receive a counter output in response to the control signal, and (ii) produce a lock status output based on the counter output. The method generally comprises the steps of (1) counting pulses of a PLL (or a periodic derivative thereof) in response to a reference clock signal, and (2) indicating a lock status based on the number of counted pulses. The present invention advantageously provides a circuit designer the ability to tune the range of acceptable frequencies by choosing an appropriate reference frequency and adjusting the decoder to produce a positive lock status for a desired range of pulse counts.

Dependencies are inferred from the claim text.