Pulsed static flip-flop
AssigneeInfineon Technologies AG
InventorsChristian Pacha, Siegmar Koppe, Karl Zapf
Life of this patent
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Abstract
A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means which hold a logic hold level to be tapped off as a stored logic state of the logic signal. The logic hold level is adjustable to a first logic level by a first push-pull transistor controlled by the set signal and to a second logic level by a second push-pull transistor controlled by the reset signal.
Claims32
A pulsed static flip-flop comprising:
- a first logic device which combines a logic signal with a pulsed signal and outputs a set signal;
- a second logic device which logically combines said logic signal with a complementary pulsed signal and outputs a reset signal;
- and
- a latch device comprising storage which holds a logic hold level to be tapped off as a stored logic state of said logic signal;
- said logic hold level being adjustable to a first logic level by a first push-pull transistor controlled by said set signal and to a second logic level by a second push-pull transistor controlled by said reset signal.
A circuit arrangement comprising
- a plurality of pulsed static flip-flop devices connected in series and each comprising a data input and a data output;
- and
- a logic circuit being coupled between a data output of a first flip-flop device of said flip-flop devices and a data input of a second flip-flop device of said flip-flop devices;
- at least one of said flip-flop devices comprising:
- a first logic device logically combining a logic signal, applied to its data input, with a pulsed signal and outputting a set signal;
- a second logic device logically combining said logic signal with a complementary pulsed signal and outputting a reset signal;
- and
- a latch device comprising storage which holds a logic hold level being fed to said data output of the relevant flip-flop as a stored logic state of said logic signal;
- said logical hold level being adjustable to a first logic level by a first push-pull transistor controlled by said set signal to a second logic level by a second push-pull transistor controlled by said reset signal.
A method comprising using a pulsed static flip-flop in a microprocessor system, the pulsed static flip-flop comprising:
- a first logic device which combines a logic signal with a pulsed signal and outputs a set signal;
- a second logic device which logically combines said logic signal with a complementary pulsed signal and outputs a reset signal;
- and
- a latch device comprising storage which holds a logic hold level to be tapped off as a stored logic state of said logic signal;
- said logic hold level being adjustable to a first logic level by a first push-pull transistor controlled by said set signal and to a second logic level by a second push-pull transistor controlled by said reset signal.
A method for storing a logic state of a logic signal utilizing a storage means which holds a hold level, comprising the steps of:
- pulling, utilizing a first switching means, said hold level to a first predetermined level if a signal transition from a first logic level to a second logic level of the logic signal occurs;
- and
- pulling, utilizing a second switching means, said hold level to a predetermined second level if a signal transition of said logic signal from said second logic level to said first logic level occurs.
Dependencies are inferred from the claim text.