DLL circuit and method of controlling the same

A delay locked loop (DLL) circuit comprising:

• a phase conversion control unit configured to receive a phase comparison signal whose level is determined by a phase relationship between a reference clock and a feedback clock, to outputs a phase conversion control signal;
• and
• a phase converting unit configured to invert a delay clock when a phase of the reference clock leads the phase of the feedback clock, to output the delay clock without inversion when a phase of the feedback clock leads the phase of the reference clock on the basis of the phase conversion control signal.

A delay locked loop (DLL) circuit comprising:

• a phase conversion control unit configured to generate first and second phase conversion control signals according to whether a frequency of an external clock exceeds a predetermined frequency;
• and
• a phase converting unit configured to control a phase of a delay clock according to whether the first phase conversion control signal or the second phase conversion control signal is enabled, to transmit the controlled delay clock to a delay compensating unit.

A delay locked loop (DLL) circuit comprising:

• a phase conversion control unit configured to generate first and second phase conversion control signals according to whether or not a plurality of CAS latency signals generated according to a length of CAS latency or a plurality of test signals are enabled;
• and
• a phase converting unit configured to invert a delay clock when the length of the CAS latency is smaller than a predetermined length and to output the inverted clock, and output the delay clock without inversion when the length of the CAS latency is equal to or larger than the predetermined length on the basis of the first and second phase conversion control signals.

A method of controlling a delay locked loop (DLL) circuit, comprising:

• latching and driving a phase comparison signal in response to input of a delay enable signal, and outputting the driven signal as a phase conversion control signal;
• and
• controlling a phase of a delay clock on the basis of the phase conversion control signal, and transmitting the controlled delay clock to a delay compensating unit.

A method of controlling a delay locked loop (DLL) circuit, comprising:

• receiving a phase comparison signal whose level is determined by the phase relationship between a reference clock and a feedback clock, and outputting a phase conversion control signal;
• and
• inverting a delay clock when a phase of the reference clock leads a phase of the feedback clock and, outputting the delay clock without inversion when the phase of the feedback clock leads the phase of the reference clock on the basis of the phase conversion control signal.

A method of controlling a delay locked loop (DLL) circuit, comprising:

• generating first and second phase conversion control signals according to whether a frequency of an external clock is larger than a predetermined frequency;
• and
• controlling a phase of a delay clock according to whether the first phase conversion control signal or the second phase conversion control signal is enabled and outputting the controlled delay clock to a delay compensating unit.

A method of controlling a delay locked loop (DLL) circuit comprising:

• generating first and second phase conversion control signals according to whether or not a plurality of CAS latency signals generated according to the length of CAS latency or a plurality of test signals are enabled;
• and
• inverting a delay clock when a length of the CAS latency is smaller than a predetermined length, and outputting the delay clock without inversion when the length of the CAS latency is equal to or larger than the predetermined length on the basis of the first and second phase conversion control signals.