Clock signal synchronizing device, and clock signal synchronizing method

Abstract

The invention relates to a clock signal synchronizing method, and to a clock signal synchronizing device (101) to be used with the synchronization of clock signals (CLK, DQS), comprising: a delay means (102) with a variably controllable delay time (tvar), in which a clock signal (CLK) or a signal obtained therefrom is input, is loaded with the variably controllable delay time (tvar), and is output as delayed clock signal, a phase comparator (104) for comparing the phase of the clock signal (CLK) or of the signal obtained therefrom with the phase of the delayed clock signal or of a signal obtained therefrom (DCLK, FB), characterized in that additionally a means (401, 116) is provided for activating and/or deactivating said clock signal synchronizing device (101) as a function of control signals (RD) evaluated by an evaluating means (402).

Dependencies are inferred from the claim text.