Transistor arrangement for rectifier and inverter
AssigneeRobert Bosch GmbH
InventorsStephan Rees, Armin Ruf, Ulrich Ammann
Life of this patent
Estimating the term…
Loading patent…
AssigneeRobert Bosch GmbH
InventorsStephan Rees, Armin Ruf, Ulrich Ammann
Estimating the term…
The invention relates to a transistor arrangement (1) comprising a transistor (10), which is provided with first and second connections (12, 14) and a control connection (16) for controlling a current flow (iD) between said first and second connections (12, 14), a signal processing device (22) exposed to the transistor control voltage (uDS) for admitting said control connection (16) according to a differential voltage (uDS) supplied between the first and second connections (12, 14) and a control device (23) which is associated with the signal processing device (22) and switches it between at least two operating modes. An inverter signal (uWR) causes, for an uWR value=0, an effect in such a way that the transistor (10) is used in the form of a conductor for uDS<0 and is locked for uDS>0. For uWR=uWR, said transistor (10) is permanently conductive.
Transistor arrangement (1) comprising a transistor (10), having a first and a second terminal (12, 14) and a control terminal (16), which sets a current flow (iD) between the first and second terminals (12, 14), and furthermore comprising a signal conditioning device (22), which applies a transistor control voltage (uGS) to the control terminal (16) in a manner dependent on a differential voltage (uDS) present between the first and second terminals (12, 14), characterized by a driving apparatus (23), which is assigned to the signal conditioning device (22) and switches the latter between at least two operating modes.
Method for controlling a transistor (10) having a first and a second terminal (12, 14) and a control terminal (16) which sets a current flow (iD) between the first and second terminals (12, 14), a transistor control voltage (uGS) being applied to the control terminal (16) in a manner dependent on a differential voltage (uDS) present between the first and second terminals (12, 14), characterized in that the transistor control voltage (uGS) is occasionally influenced by a voltage independent of the differential voltage (uDS).
Dependencies are inferred from the claim text.