Reducing Pin Count When the Digital Output is to be Provided in Differential or Single-ended Form

An integrated circuit comprising:

• a first pin and a second pin;
• a first buffer designed to provide a first sequence of digital values in single-ended form on said first pin;
• a second buffer designed to provide a second sequence of digital values also in single-ended form but on said second pin;
• and
• a third buffer designed to provide a third sequence of digital values in a differential form across said first pin and said second pin,
• wherein said third buffer provides said third sequence of digital values at a frequency twice that at which said first buffer provides said first sequence of digital values and said second buffer provides said second sequence of digital values,
• wherein said first pin and said second pin are package pins of said integrated circuit.

A method of providing digital values on pins of an integrated circuit to an external component, said method comprising:

• providing a first sequence of digital values on a first pin and a second sequence of digital values on a second pin if said digital values are to be provided to said external component in a singled ended form;
• and
• providing a third sequence of digital values in a differential form across said first pin and said second pin if said digital values are to be provided to said external component in a differential form,
• wherein said third sequence of digital values are provided at a frequency twice that at which each of said first sequence of digital values and said second sequence of digital values is provided,
• wherein said first pin and said second pin are package pins of said integrated circuit.

An apparatus for providing digital values on pins to an external component, said apparatus being contained in an integrated circuit, said apparatus comprising:

• means for providing a first sequence of digital values on a first pin and a second sequence of digital values on a second pin if said digital values are to be provided to said external component in a singled ended form;
• and
• means for providing a third sequence of digital values in a differential form across said first pin and said second pin if said digital values are to be provided to said external component in a differential form,
• wherein said third sequence of digital values are provided at a frequency twice that at which said first sequence of digital values is provided and said second sequence of digital values is provided,
• wherein said first pin and said second pin are package pins of an integrated circuit.

A system comprising:

• an integrated circuit providing a digital code, said integrated circuit comprising:
• a first pin and a second pin, wherein said first pin and said second pin are package pins of said integrated circuit;
• a first buffer designed to provide a first sequence of digital values in single-ended form on said first pin;
• a second buffer designed to provide a second sequence of digital values also in single-ended form but on said second pin;
• and
• a third buffer designed to provide a third sequence of digital values in a differential form across said first pin and said second pin,
• wherein said third buffer provides said third sequence of digital values at a frequency twice that at which said first buffer provides said first sequence of digital values and said second buffer provides said second sequence of digital values,
• wherein said digital code is one of said first sequence of digital values, said second sequence of digital values and said third sequence of digital values;
• and
• a processing unit processing said digital code.