AND type match circuit structure for content-addressable memories

Abstract

This invention provides An AND type match circuit structure for content-addressable memories adopting the Pseudo-Footless Clock-and-Data Pre-charged Dynamic circuit as an AND type match circuit structure, which comprises a plurality of circuit stages. Each circuit stage connects a CMOS to a plurality of NMOS in series, wherein the CMOS is connected to the input of an inverter and a PMOS that is in parallel to the inverter, and the output of the inverter is connected to the CMOS gate of the next circuit stage. The output of the last stage inverter on the Pseudo-Footless Clock-and-Data Pre-charged Dynamic circuit is connected to an AND gate logic circuit. When the AND type match circuit structure is applied to the content-addressable memories of low power consumption and high match speed, the circuit structure is able to increase match speed significantly, and to develop the compiler for the content-addressable memories

Dependencies are inferred from the claim text.