Input buffer with optimal biasing and method thereof
AssigneeMicron Technology, Inc.
InventorDragos Dimitriu
Life of this patent
Estimating the term…
Abstract
A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averaging of the differential internal signals. The input buffer further includes a second stage coupled to the differential internal signals and configured to generate differential output signals. A memory device includes a memory array with the respective input buffer. Differential input signals are received and differential internal signals are generated as biased in response to an averaging of the differential internal signals. Differential output signals are generated in a second stage from the differential internal signals.
Claims34
An input buffer, comprising:
- a first stage for receiving differential input signals and generating differential internal signals controlled by a bias voltage in response to averaging of the differential internal signals;
- and
- a second stage coupled to the differential internal signals and configured to generate differential output signals.
A memory device, comprising:
- a memory array including a plurality of memory cells;
- and
- at least one input buffer, including:
- a first stage for receiving differential input signals and generating differential internal signals controlled by a bias voltage in response to an averaging of the differential internal signals;
- and
- a second stage coupled to the differential internal signals and configured to generate differential output signals.
An electronic system, comprising:
- a processor;
- and
- a memory device operatively coupled to the processor, the memory device comprising:
- a memory array including a plurality of memory cells;
- and
- an input buffer, including:
- a first stage for receiving differential input signals and generating differential internal signals as controlled by a bias voltage in response to an averaging of the differential internal signals;
- and
- a second stage coupled to the differential internal signals and configured to generate differential output signals.
A method of buffering an input signal, comprising:
- receiving differential input signals and generating differential internal signals as biased in response to an averaging of the differential internal signals at a first stage;
- and
- generating differential output signals in a second stage from the differential internal signals.
A semiconductor substrate having a surface on which an input buffer is fabricated, the input buffer comprising:
- a first stage for receiving differential input signals and generating differential internal signals as biased in response to an averaging of the differential internal signals;
- and
- a second stage coupled to the differential internal signals and configured to generate differential output signals.
Dependencies are inferred from the claim text.