Data input/output circuit and method of semiconductor memory apparatus
AssigneeHynix Semiconductor Inc.
InventorSeung-Lo Kim
Life of this patent
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Abstract
A first timing control unit controls an active timing of a first control signal to output a first driving control signal. A first data input/output unit transmits write data from a data input/output buffer to a global input/output line or transmits read data from the global input/output line to the data input/output buffer, in response to the first driving control signal. A second timing control unit controls an active timing of a second control signal to output a second driving control signal. A second data input/output unit transmits the write data from the global input/output line to a local input/output line or transmits the read data from the local input/output line to the global input/output line, in response to the second driving control signal.
Claims23
A data input/output circuit of a semiconductor memory apparatus, comprising:
- a first timing control unit configured to control an active timing of a first control signal to output a first driving control signal;
- a first data input/output unit configured to transmit write data from a data input/output buffer to a global input/output line, or transmit read data from the global input/output line to the data input/output buffer, in response to the first driving control signal;
- a second timing control unit configured to control an active timing of a second control signal to output a second driving control signal;
- and
- a second data input/output unit configured to transmit the write data from the global input/output line to a local input/output line, or transmit the read data from the local input/output line to the global input/output line, in response to the second driving control signal.
A data input/output method of a semiconductor memory apparatus that outputs read data to a first read driver group that is half of a plurality of read drivers and a second driver group that is a remaining half of the plurality of read drivers through global input/output lines during a read operation when the read data is read out from memory cells through the plurality of read drivers, comprising:
- producing a first timing control signal and a second timing control signal by controlling an active timing of a read driver control signal;
- outputting the read data to the global input/output lines through the first read driver group in response to the firs timing control signal, after a read command is input to the semiconductor memory apparatus;
- and
- outputting the read data to the global input/output lines through the second read driver group in response to the second timing control signal after a predetermined time.
A data input/output method of a semiconductor memory apparatus that stores the write data in a plurality of latch units, inputs the write data to global input/output lines through a plurality of input drivers, and inputs the write data from the global input/output lines to a plurality of write drivers, during a write operation that stores write data input from a data input/output buffer in memory cells in response to an input driver control signal and a write driver control signal, wherein the latch units are divided into a first latch unit group including half the latch units and a second latch unit group including the other half the latch units and the write drivers are divided into a first write driver group including half the write drivers and a second write driver group including the other half the write drivers, the method comprising:
- outputting the write data stored in the first latch unit group to the global input/output lines through the plurality of input drivers for a time corresponding to half a burst length in response to the input driver control signal after a write command is issued;
- inputting the write data from the global input/output lines to the first write driver group in response to the write driver control signal;
- outputting the data stored in the second latch unit group to the global input/output lines through the plurality of input drivers for a time corresponding to half the burst length in response to the input driver control signal that is delayed for a predetermined time;
- and
- inputting the write data from the global input/output lines to the second write driver group in response to the delayed write driver control signal.
Dependencies are inferred from the claim text.