Voltage level shifter circuit
AssigneeMosaid Technologies Incorporated
InventorValerie Lines
Life of this patent
Estimating the term…
Abstract
A level shifter circuit for converting a logic signal with logic ‘1’ and ‘0’ levels at first high and low supply voltage levels to a signal with second high and low supply voltage levels. In particular, the second high and low supply voltage levels are greater than the first high and low supply voltage levels. The disclosed level shifter is configured such that the size of the preceding logic gate and circuitry within the level shifter can be reduced, facilitating its layout in pitch-limited areas. The level shifter also includes circuitry to decouple the output pull-up and pull-down paths to further facilitate state transitions and reduce crowbar current consumption.
Claims9
A level shifter circuit to translate a logic signal with logic ‘1’ and ‘0’ levels corresponding to first high and low voltage levels, driven from a logic circuit powered by first high and low voltage supplies, to an output signal with second high and low voltage levels, comprising:
- a first circuit receiving a second high voltage supply for providing the second high voltage level to the output signal in response to a first state of the logic signal;
- a second circuit receiving a second low voltage supply for providing the second low voltage level to the output signal in response to the second state of the logic signal;
- and,
- a crowbar current limiting circuit connected to the output signal between the first circuit and the second circuit for limiting crowbar current between the first circuit and the second circuit during a state transition of the logic signal.
A level shifter circuit to translate an input logic signal with logic ‘1’ and ‘0’ levels corresponding to first high and low voltage levels driven from a logic circuit powered by first high and low voltage supplies, to an output signal with second high and low voltage levels, comprising:
- a first p-channel transistor having a source connected to a second high voltage supply;
- a second p-channel transistor having a source connected to the second high voltage supply, a drain connected to a gate of the first p-channel transistor and a gate connected to the output signal;
- a first n-channel transistor having a drain connected to the drain of the second p-channel transistor, a source connected to the first low voltage supply and a gate connected to a first logic signal with the first high and low voltage levels;
- a third p-channel transistor connected between a drain of the first p-channel transistor and the output signal, the third p-channel transistor having a gate connected to a second logic signal with the first high and low logic voltage levels;
- a second n-channel transistor having a source connected to a second low voltage supply;
- a third n-channel transistor having a source connected to the second low voltage supply, a drain connected to a gate of the second n-channel transistor, and a gate connected to the output signal;
- a fourth p-channel transistor having a drain connected to the gate of the second n-channel transistor, a source connected to the first high voltage supply and a gate connected to the first logic signal with the first high and low voltage levels;
- and,
- a fourth n-channel transistor connected between the drain of the second n-channel transistor and the output signal, and a gate connected to the second logic signal with the first high and low logic voltage levels.
Dependencies are inferred from the claim text.