Capacitor-coupled level shifter with duty-cycle independence
AssigneeAvnera Corporation
InventorPatrick Quinn
Life of this patent
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Abstract
A circuit architecture, or topology, that provides a level shifter which is substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled inputs terminals connected to the gates of the high-side (i.e., connected to the positive power supply) transistors and a pair of voltage dividers to set the bias voltage at the gates of the high-side transistors, wherein one side of each voltage divider is coupled to the power supply node and the other side of each voltage divider is cross-coupled to the output node of the opposite side of the H-bridge.
Claims20
A circuit, comprising:
- an H-bridge arrangement of field effect transistors, including a pair of high-side transistors connected to a power supply node, the H-bridge having a pair of output nodes, each output node disposed on an opposite side of the H-bridge;
- a first pair of input terminals, each of the first pair of input terminals capacitively coupled to a respective one of the high-side transistors;
- and
- a pair of voltage dividers, wherein one side of each voltage divider is coupled to the power supply node, and the other side of each voltage divider is cross-coupled to the output node of the opposite side of the H-bridge.
A level-shifter circuit, comprising:
- a first PFET coupled source-to-drain between a first power supply node and a first intermediate node;
- a first NFET coupled drain-to-source between the first intermediate node and a second power supply node;
- a second PFET coupled source-to-drain between the first power supply node and a second intermediate node;
- a second NFET coupled drain-to-source between the second intermediate node and the second power supply node;
- a first resistor coupled between the first power supply node and a gate electrode of the first PFET;
- a second resistor coupled between the gate electrode of the first PFET and the second intermediate node;
- a third resistor coupled between the first power supply node and a gate electrode of the second PFET;
- and
- a fourth resistor coupled between the gate electrode of the second PFET and the first intermediate node.
A method, comprising:
- providing a bias network, the bias network having an output node, and operable to provide a bias signal at the bias network output node;
- providing a first switching element, the first switching element having a control terminal coupled to the bias network output node, the first switching element further having a terminal coupled to a first power supply node, the first power supply node providing a first supply voltage;
- capacitively coupling a signal onto the control terminal, the signal having a first voltage swing, and further having a first duty cycle;
- wherein the output of the bias signal varies such that an output of the first switching element is substantially independent of the first duty cycle.
Dependencies are inferred from the claim text.