Efficient configuration of daisy-chained programmable logic devices

A method of configuring at least one programmable logic device (PLD), comprising:

• receiving a signal indicating a number of serial interface memories coupled to the at least one PLD;
• gating a PLD read clock according to the number to provide a serial read clock to the serial interface memories;
• and
• receiving a compressed configuration bitstream from each of the number of serial interface memories in response to the serial read clock.

A programmable logic device, comprising:

• a memory interface adapted to receive a first address signal from an external source;
• configuration memory cells adapted to store a second address signal;
• and
• an SPI processor adapted to select either the first address signal or the second address signal and to provide the selected address as a leading read address to at least one SPI flash memory.

A system comprising:

• a plurality of serial interface memory devices, each adapted to store a configuration bitstream;
• a master field programmable gate array (FPGA) coupled to the plurality of serial interface memories to receive their bistreams, the master PLD including:
• a multiplexer adapted to select the configuration bitstream from each of the plurality serial interface memories;
• and
• a serial interface processor adapted to command the bitstream selection by the multiplexer;
• and
• one or more slave FPGAs daisy chained to the master FPGA and adapted to receive a configuration bitstream from the master FPGA.