Configurations and method for carrying out wafer level unclamped inductive switching (UIS) tests

A circuit for performing an unclamped inductive test on a metal oxide semiconductor field effect transistor (MOSFET) device comprising:

• a controllable switch for switching OFF a power supply to said MOSFET device upon detection of a MOSFET failure under said UIS test for limiting a current passing through said MOSFET device during said MOSFET failure to an UIS current to prevent damages to an UIS testing probe.

An array of test circuits comprising at least a first and second test circuits wherein each test circuit is for performing an unclamped inductive test on a first and a second metal oxide semiconductor field effect transistor (MOSFET) devices, wherein each of said test circuits comprising:

• a controllable switch for switching OFF a power supply to said first or second MOSFET devices upon detection of a MOSFET failure under said UIS test for limiting a current passing through said first or second MOSFET devices during said MOSFET failure to an UIS current to prevent damages to an UIS testing probe.

A method for performing an unclamped inductive test on a metal oxide semiconductor field effect transistor (MOSFET) device driven by a gate driver comprising:

• measuring an unclamped inductive testing (UIS) current by using a current sense circuit while increasing said UIS current by continuously applying a gate driving pulse from said gate driver to said MOSFET device;
• and
• turning off said gate driver when a predefined UIS current is measured by said current sensing circuit.

A method for performing an unclamped inductive test on a metal oxide semiconductor field effect transistor (MOSFET) device comprising:

• controlling a switch for switching OFF a power supply to said MOSFET device upon detection of a MOSFET failure under said UIS test for limiting a current passing through said MOSFET device during said MOSFET failure to an UIS current to prevent damages to an UIS testing probe.

A method for simultaneously performing an unclamped inductive switch (UIS) test on at least a first and a second metal oxide semiconductor field effect transistor (MOSFET) devices in parallel by using an array of test circuits comprising at least a first and second test circuits, said method comprising:

• switching OFF a power supply to said first or second MOSFET devices upon detection of a MOSFET failure under said UIS test for limiting a current passing through said first or second MOSFET devices during said MOSFET failure to an UIS current to prevent damages to an UIS testing probe.