Wafer level chip scale package (WLCSP) with high reliability against thermal stress
AssigneeHynix Semiconductor Inc.
InventorsJong Hoon Kim, Min Suk Suh, Chang Jun Park, Kwon Whan Han, Seong Cheol Kim
Life of this patent
Estimating the term…
Abstract
A wafer level chip scale package includes a semiconductor chip having a plurality of pads; a lower insulation layer having a high Young's modulus of 1˜5 GPa formed on the semiconductor chip to expose the plurality of pads; a plurality of metal patterns formed on the lower insulation layer to be connected to the respective pads; an upper insulation layer having a high Young's modulus of 1˜5 GPa formed on the lower insulation layer and the metal patterns to partially expose the metal patterns; and a plurality of solder balls formed on exposed portions of the metal patterns.
Claims5
A wafer level chip scale package comprising:
- a semiconductor chip having a plurality of pads;
- a lower insulation layer having a high Young's modulus in the range of 1-5 GPa formed on the semiconductor chip to expose the plurality of pads;
- a plurality of metal patterns formed on the lower insulation layer, each metal pattern connected to one of the pads;
- a upper insulation layer having a high Young's modulus in the range of 1-5 GPa formed on the lower insulation layer and the metal patterns to partially expose the metal patterns;
- and
- a plurality of solder balls formed on the exposed portions of the metal patterns.
Dependencies are inferred from the claim text.