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US 2007/0182013 A1Published application
Damascene structure having a reduced permittivity and manufacturing method thereof
AssigneesShanghai Ic R&D Center Co., Ltd, Shanghai Huahong (Group) Co., Ltd
InventorJun Zhu
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Abstract
A semiconductor device includes a damascene structure and an air gap embedded in the damascene dielectric layer. A method of manufacturing a semiconductor device includes depositing a metal barrier in advance as an etch stop, forming a copper damascene interconnect structure, forming an air gap, and depositing a photosensitive passivation material on the air gap.
Claims16
A semiconductor device, comprising:
- an etch barrier layer;
- a dielectric layer over the etch barrier layer;
- a conductive metal interconnect formed in a first region of the semiconductor device and though the dielectric layer and etch barrier;
- a metal barrier layer formed in a second region of the semiconductor device different from the first region and over the etch barrier layer;
- an air gap formed in the second region and extending through the dielectric layer and to the metal barrier layer;
- an upper photosensitive passivation material formed at least over a top portion of the air gap;
- and
- a photosensitive passivation material formed at a bottom portion of the air gap on the metal barrier layer.
5 more elements
A method of manufacturing a semiconductor device, comprising:
- forming an etch barrier layer;
- forming a dielectric layer on the etch barrier layer;
- forming a metal barrier layer over the etch barrier layer in a first region;
- forming a metal interconnection through the dielectric layer and the etch barrier layer in a second region different from the first region;
- forming a metal passivation layer on an uppermost portion of the metal interconnection;
- applying and patterning a first photosensitive material on the met passivation layer;
- etching the metal passivation layer using the patterned first photosensitive material to expose the uppermost portion of the metal interconduction;
- removing the patterned first photosensitive material;
- applying and patterning a second photosensitive material on the metal passivation layer and the exposed uppermost portion of the metal interconnection;
- etching the first region to form an air gap extending to the metal barrier layer, the first region being substantially free of metal interconnections;
- removing the patterned second photosensitive material;
- applying a photosensitive passivation material on the air gap;
- etching the photosensitive passivation material to expose the uppermost portion of the metal interconnection;
- and
- baking the semiconductor device.
12 more elements
Dependencies are inferred from the claim text.