Semiconductor device, reticle used in fabricating method for the same and fabrication method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung-woo Cho, Sang-hoon Park
Life of this patent
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Abstract
A semiconductor device may include a substrate and a dielectric layer may be formed on the substrate. A multi-layered interconnection structure may be embedded in the dielectric layer. A plurality of bonding pads, which may be connected to an uppermost interconnection layer of the multi-layered interconnection structure, may be spaced apart in a first direction. A passivation layer may have a plurality of bonding pad openings that may be defined by a plurality of slits and respectively expose the bonding pads. The slits may overlap isolations of the bonding pads. Each of the slits may have an edge width that may be larger than a center width thereof.
Claims21
A semiconductor device comprising:
- a substrate;
- a dielectric layer provided on the substrate;
- a multi-layered interconnection structure embedded in the dielectric layer;
- a plurality of bonding pads connected to an uppermost interconnection layer of the multi-layered interconnection structure, the bonding pads spaced apart in a first direction;
- and
- a passivation layer having a plurality of bonding pad openings, the bonding pad openings being defined by a plurality of slits and respectively exposing the bonding pads, the slits overlapping isolations of the bonding pads and an edge width of the slits being larger than a center width of the slits.
A reticle formed on a substrate through which exposure light is transmittable comprising:
- a light shield layer with a plurality of light transmitters that are spaced apart in a first direction and are rectangles with chamfered or rounded corners.
A method of fabricating a semiconductor device, the method comprising:
- providing a substrate;
- forming a dielectric layer on the substrate, a multi-layered interconnection structure being embedded in the dielectric layer;
- forming a plurality of bonding pads connected to an uppermost interconnection layer of the multi-layered interconnection structure, the bonding pads being spaced apart in a first direction;
- and
- forming a passivation layer having a plurality of bonding pad openings, the bonding pad openings being defined by a plurality of slits and respectively exposing the bonding pads, the slits overlapping isolations of the bonding pads and an edge width of the slits being larger than a center width of the slits.
A semiconductor device comprising:
- a substrate supporting a plurality of bonding pads;
- and
- a passivation layer provided on the substrate, the passivation layer having a plurality of bonding pad openings respectively exposing the bonding pads, the bonding pad openings being defined by a plurality of slits, an edge width of the slits being larger than a center width of the slits;
- the pitch of the bonding pad openings being 60 μm or less;
- and
- a ratio between (1) the pitch of the bonding pad openings and (2) a minimum isolation distance between adjacent bonding pad openings being greater than 2.5.
Dependencies are inferred from the claim text.