Stacked semiconductor device
AssigneeElpida Memory, Inc.
InventorsMasakazu Ishino, Hiroaki Ikeda, Junji Yamada
Life of this patent
Estimating the term…
Abstract
A stacked semiconductor device includes an interposer substrate having external power supply terminals, and semiconductor chips stacked on the interposer substrate. A power supply wiring arranged in the semiconductor chip located in the bottom layer is connected to the external power supply terminal via a bump electrode, the power supply wiring arranged in the semiconductor chip located in the top layer is connected to the external power supply terminal via a bonding wire, and the power supply wirings each arranged in adjacent semiconductor chips are mutually connected via the through electrode. Such a loop structure can solve a problem such that the higher the semiconductor chip, the larger its voltage drop.
Claims20
A stacked semiconductor device in which a plurality of semiconductor chips including at least first and second semiconductor chips are stacked, comprising:
- an external power supply terminal;
- a first connection means that electrically connects a power supply wiring arranged in the first semiconductor chip and the external power supply terminal;
- a second connection means that electrically connects a power supply wiring arranged in the second semiconductor chip and the external power supply terminal;
- and
- a third connection means that mutually electrically connects the power supply wirings each provided in adjacent semiconductor chips.
A stacked semiconductor device, comprising:
- a plurality of stacked semiconductor chips;
- and
- a power supply wiring that supplies a power supply potential to the plurality of semiconductor chips, wherein
- the power supply wiring has a loop structure that includes a portion that goes through a through electrode arranged in the plurality of semiconductor chips, and a portion that goes through at least one bypass conductor.
A stacked semiconductor device, comprising:
- a plurality of stacked semiconductor chips;
- means for supplying a power supply potential in a cascade manner to the plurality of semiconductor chips from a side of a bottom-layered semiconductor chip among the plurality of semiconductor chips;
- and
- means for supplying a power supply potential in a cascade manner to the plurality of semiconductor chips from a side of a top-layered semiconductor chip among the plurality of semiconductor chips.
Dependencies are inferred from the claim text.