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US 2007/0181951 A1Published application
Selective CESL structure for CMOS application
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Lin Chen, Min-Jan Chen, Jau-Jey Wang
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Abstract
A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.
Claims17
A semiconductor structure comprising:
- a PMOS device comprising:
- a first gate structure over a substrate;
- a first gate spacer on a sidewall of the first gate structure;
- a first source/drain region substantially aligned with a side edge of the first gate spacer;
- a barrier layer over at least a portion of the first gate structure, the first gate spacer, and the first source/drain region, wherein the barrier layer is formed by a process generating substantially no hydrogen-containing by-products;
- and
- a first stressed contact etch stop layer over the barrier layer;
- and
- an NMOS device comprising:
- a second gate structure over the substrate;
- a second gate spacer on a sidewall of the second gate structure;
- a second source/drain region substantially aligned with a side edge of the second gate spacer;
- and
- a second stressed contact etch stop layer having a tensile stress over at least a portion of the second gate structure, the second gate spacer, and the second source/drain region, wherein the barrier layer is substantially not located under the second stressed contact etch stop layer.
11 more elements
A semiconductor structure comprising:
- a substrate comprising a first region and a second region;
- and
- a PMOS device in the first region, wherein the PMOS device comprises:
- a first gate structure over the substrate in the first region;
- a first gate spacer on a sidewall of the first gate structure;
- a first source/drain region comprising a p-type impurity substantially aligned with a side edge of the first gate spacer;
- an oxide layer over the first gate structure, the first gate spacer, and the first source/drain region, wherein the oxide layer is formed by a process generating substantially no hydrogen-containing by-product;
- and
- a first contact etch stop layer over the barrier layer wherein the first contact etch stop layer is formed in a process generating a hydrogen-containing by-product.
6 more elements
Dependencies are inferred from the claim text.