Semiconductor device and its manufacturing method capable of suppressing junction leakage current

A method for manufacturing a semiconductor device comprising;

• forming a gate insulating layer on a semiconductor substrate;
• forming a gate electrode layer on said gate insulating layer;
• forming a source region and a drain region within said semiconductor substrate adjacent to said gate electrode layer;
• forming sidewall insulating layers on sidewalls of said gate electrode layer and said gate insulating layer;
• forming air gaps between one of said sidewall insulating layers and said source region and between another of the sidewall insulating layers and said drain region;
• forming semiconductor layers on said source region and said drain region outside of said air gaps, upper surfaces of said semiconductor layers being higher than upper surfaces of said air gaps;
• and
• forming silicide layers on said semiconductor layers.

A method for manufacturing a semiconductor device including a p-channel MOS transistor and an n-channel MOS transistor, comprising;

• forming first and second gate insulating layers on a semiconductor substrate for said p-channel MOS transistor and said n-channel MOS transistor, respectively;
• forming first and second gate electrode layers on said first and second gate insulating layers;
• forming a source region and a drain region of said p-channel MOS transistor within the semiconductor substrate adjacent to said first gate electrode layer and a source region and a drain region of said p-channel MOS transistor within said semiconductor substrate adjacent to said second gate electrode layer;
• and
• forming first sidewall insulating layers of a multi-layer structure of SiO2 and SiN on sidewalls of said first gate electrode layer and said first gate insulating layer, and second sidewall insulating layers of said multi-layer structure of SiO2 and SiN on sidewalls of said second gate electrode layer and said second gate insulating layer;
• forming air gaps between one of said first sidewall insulating layers and said source region of said p-channel MOS transistor and between another of said first sidewall insulating layers and said drain region of said p-channel MOS transistor;
• forming semiconductor layers on said source region and said drain region of said p-channel MOS transistor outside of said air gaps, upper surfaces of said semiconductor layers being higher than upper surfaces of said air gaps;
• and
• forming silicide layers on said semiconductor layers of said p-channel MOS transistor and said source region and said drain region of said n-channel MOS transistor.