Thermal isolation of phase change memory cells

A memory comprising:

• an array of resistive memory cells;
• bit lines coupled to each of the memory cells;
• and
• a conductive perforated plate surrounding the memory cells for accessing the memory cells.

A semiconductor memory device comprising:

• an array of phase-change memory cells, each memory cell including a transistor and a memory element, one side of a source-drain path of each transistor coupled to a memory element;
• bit lines coupled to each of the memory elements;
• and
• a ground plate coupled to the other side of the source-drain path of each transistor.

A method for fabricating a memory, the method comprising:

• providing an array of resistive memory cells;
• providing bit lines between rows of the memory cells for accessing the memory cells;
• and
• providing a conductive plate coupled to each of the memory cells.

A method for fabricating a memory, the method comprising:

• providing an array of resistive memory cells;
• providing bit lines coupled to each of the memory cells;
• and
• providing a perforated conductive plate for accessing the memory cells.