Semiconductor Constructions, Memory Cells, DRAM Arrays, Electronic Systems; Methods of Forming Semiconductor Constructions; and Methods of Forming DRAM Arrays

A semiconductor construction comprising:

• a contact plug having an upper surface;
• a first bottom plate in electrical contact with the upper surface and extending vertically upward to a first elevation relative to the upper surface;
• a second bottom plate spaced from the first bottom plate by a distance;
• and
• an insulative support structure spanning the distance between the first and second bottom plates at a second elevation between the upper surface and the first elevation.

A DRAM array comprising:

• a first row of contact plugs;
• a second row of contact plugs spaced from the first row of contact plugs by a first distance;
• a third row of contact plugs spaced from the second row of contact plugs by a second distance, the second distance being greater than the first distance;
• and
• a first plurality of bottom plates, each bottom plate comprised by the first plurality being in electrical contact with a single contact plug and spanning the second distance, the single contact plug being within the second row of contact plugs.

An electronic system comprising:

• a processor;
• and
• a memory devise operably associated with the processor, the memory device having a memory array comprising:
• a first row of contact plugs;
• a second row of contact plugs spaced from the first row of contact plugs by a first distance;
• a third row of contact plugs spaced from the second row of contact plugs by a second distance which is greater than the first
• a plurality of bottom capacitor plates spanning the second distance, each contact plugs comprised by the second row being electrically connected to a single of the bottom capacitor plates comprised by the plurality of bottom capacitor plates.