Non-volatile memory device and method of fabricating the same

A non-volatile memory device comprising:

• a symmetrical pair of floating gate/control gate structures simultaneously formed around a common source region disposed in a semiconductor substrate;
• wherein each one of the symmetrical pair of floating gate/control gate structures comprises:
• a gate insulating film formed on the semiconductor substrate;
• a floating gate completely covering the gate insulating film, the floating gate comprising a conductive film pattern and a conductive spacer formed at one side of the conductive film pattern;
• a tunnel insulating film formed on a portion of the conductive film pattern, the conductive spacer, and extending laterally outward over a portion of the semiconductor substrate adjacent the conductive spacer;
• and
• a control gate formed on the tunnel insulating film.

A method of fabricating a non-volatile memory device, the method comprising:

• forming a gate insulating film on the semiconductor substrate;
• forming a floating gate pattern on the gate insulating film, wherein the floating gate pattern comprises a first conductive film pattern and conductive spacers formed on opposing side walls of the first conductive film pattern;
• patterning the gate insulating film by using the floating gate pattern as an etch mask;
• sequentially forming a tunnel insulating film and a second conductive film on the semiconductor substrate including the floating gate pattern;
• forming paired spaced apart control gates on the floating gate pattern, wherein each control gate comprises a portion covering a portion of the first conductive film pattern, one of the conductive spacers, and extending laterally outward over a portion of the semiconductor substrate adjacent the one conductive spacer;
• and
• forming a symmetrical pair of floating gates from the floating gate pattern by sequentially etching a portion of the floating gate pattern and the gate insulating film using the paired control gates as an etch mask;
• forming a first impurity region in the semiconductor substrate between the symmetrical pair of the floating gates;
• and
• forming a second impurity region in the semiconductor substrate proximate one side of each control gate disposed laterally outward from the first impurity region.