Integrated Circuit Device

A method of commercially mass-producing a solid state integrated circuit (IC) containing within one cubic millimeter therein over a number of active circuit components, said number being selected from the group consisting of five, kilo, mega, giga, and tera, comprising:

• supplying a solid substrate having a top surface;
• supplying a solid state material layer to position on the top surface of said solid substrate;
• said solid state material layer having, at a selected portion thereof, a width selected from the group consisting of several nanometers, several molecules, and several atoms;
• said width having an accuracy selected from the group consisting of a few nanometers and several atoms;
• and continuously and sufficiently perfectly bonding, metallurgically and atom to atom, said solid state material layer to said solid substrate to provide a commercially viable yield of said integrated circuit.

A method for commercially mass-producing a miniaturized integrated circuit (IC) containing within one cubic millimeter therein over a number of active circuit components, said number being selected from the group consisting of five, kilo, mega, giga, and tera, comprising:

• supplying a solid substrate having a first polarity;
• supplying at least two solid state material bodies for placement on said so lid substrate and having a second polarity that is opposite to said first polarity;
• providing at least two signal-translating, electronic rectifying barriers between said solid substrate and said at least two solid state material bodies;
• and
• forming an electrically insulating, solid groove to have an electrical conductivity at least one orders of magnitude different from those of said solid substrate and said solid state material bodies;
• said solid groove laterally adjoining said solid substrate while contacting and enclosing said rectifying barriers and said second solid state material bodies and, together with said rectifying barriers, electrically isolating a selected active circuit component in said miniaturized integrated circuit from another neighboring active circuit component, thereby making these two active circuit components electrically independently operable on said miniaturized integrated circuit;
• at least a selected portion of said at least two solid state material bodies having a width selected from the group consisting of several nanometers, several molecules, and several atoms;
• and
• said width having an accuracy selected from the group consisting of a few molecules and several atoms.

A method as in claim 104 including:

• using said NMAEM system on said object:
• storing software and digital information in said NMAEM system;
• receiving telecommunicated signals from outside of said object;
• and
• performing real-time computerized experiments for studying selected actions or reactions of said object so that said object always operates optimally.

A method as in claim 104 including:

• using said NMAEM system by a learning or training object in a learning or training task;
• storing software and digital information related to said learning or training task with said NMAEM system;
• receiving telecommunicated signals from outside of said object;
• and
• performing real-time computerized learning or training experiments for studying learning speed and accuracy of said object in said learning or training task relative to a number of other learning objects and environmental variables to always determine and set at an optimal learning procedure and environmental conditions whereby performance of said learning object is always optimized.

A commercially mass-producing a solid state device containing within one cubic millimeter therein over a number of active circuit components, said number being selected from the group consisting of five, kilo, mega, giga, and tera, comprising:

• supplying a first solid state material of a first conductivity type;
• supplying a second solid state material of a second conductivity type and positioned on said first solid state material;
• said first and second solid state materials having respective adjoining regions;
• providing a signal-translating, rectifying barrier at said respective adjoining regions between said first and second solid state materials;
• forming a solid isolating groove starting in said second solid state material, extending downward to pass through said rectifying barriers, and entering into said first solid state material for, in combination with the rectifying barriers, electrically isolating said multiple active device components from one another;
• forming said isolating groove to have a shape selected from the group consisting of rounded, cylindrical, ellipsoidal, paraboloidal, and conical or V-shape;
• intentionally designing and producing a curvature on a bottom of said isolating groove to eliminate wasteful central flat portion of groove bottom for inert isolating groove in prior art devices thereby avoiding harmful mismatch stresses and related problems of microcrack formation and carrier mobility variations;
• including forming said isolating groove to achieve thereon at least one of following results:
• a) being accurate to less than several nanometers in a dimension selected from the group consisting of shape, size, depth, and chemical composition profiling;
• b) containing a centrally rounded groove bottom having a smooth and non-abrupt change of radii of curvature thereon to avoid notch effects;
• c) containing a centrally rounded groove bottom having a smooth and non-abrupt change of radii of curvature thereon to avoid notch effects;
• d) having a groove bottom depth as close to zero below said rectifying barrier as possible consistent with a manageable device yield;
• e) being deep but narrow and having an aspect ratio of over 5;
• f) having a rounded bottom meeting said rectifying barrier thereby maximizing curved peripheral surface expansion across said rectifying barrier for improving device yield and performance;
• and g) having a central inverted-arch shaped, groove bottom to enhance device reliability;
• increase yield;
• decrease cost;
• improve junction surface passivation;
• increase packing density and device switching speed;
• reduce noise, instability, leakage current, and electrical shorts;
• improve breakdown voltage;
• control carriers generation, movement, and recombination at or near the rectifying barrier peripheral surface;
• and regulate optoelectromagnetic interaction of said rectifying barrier with an ambient or contacting material.

A method for commercially mass-producing a miniaturized IC semiconductor device containing within one cubic millimeter therein over a number of transistors, said number being selected from the group consisting of five, kilo, mega, giga, and tera, comprising:

• supplying a first semiconductor body having a first polarity;
• supplying a second semiconductor body located generally vertically above said first semiconductor body and having a second polarity that is opposite to the first polarity;
• providing a signal-translating, electronic rectifying barrier between said first and second semiconductor bodies;
• and
• forming an isolating groove having an electrical conductivity at least one order of magnitude different form those of said first and second

A commercially mass-producing, low-cost miniaturized integrated circuit device containing within one cubic millimeter therein over a number of transistors, said number being selected from the group consisting of five, kilo, mega, giga, and tera, comprising:

• supplying a first solid state material of a first conductivity type;
• supplying a second solid state material of a second conductivity type and positioned on said first solid state material;
• said first and second solid state materials having respective adjoining portions;
• providing a signal-translating, rectifying barrier positioned between said respective adjoining portions;
• forming an elongated, solid isolating groove starting on said second solid state material and extending toward said rectifying barrier to form a bottom which is nanometers within a selected point inside said rectifying barrier;
• and
• locating said multiple transistors, and not said isolating groove, to occupy a major portion of a top surface area of device chip thereby achieving radically improved, device miniaturization;
• and
• forming all said multiple transistors to have no centrally large and flat bottoms as in oxidized isolating groove bottoms of Peltzer and Murphy devices, thereby achieving improved device miniaturization.