Transistor
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorKiyoshi Kato
Life of this patent
Estimating the term…
Abstract
A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode 604 sandwiched therebetween, one of the impurity regions has respective contact holes (a first contact hole 601 and a second contact hole 602) and the other impurity region has a contact hole (a third contact hole 603), and contacts of the contact holes 601 to 603 or regions 605 to 607 each including a margin for a contact are arranged so as to be a triangular lattice except for the gate electrode 604.
Claims20
An electronic device comprising a transistor, the transistor comprising:
- an active region including a first impurity region and a second impurity region;
- a gate electrode adjacent to the active region;
- a first wiring electrically connected to the first impurity region via a first contact hole;
- and
- a second wiring electrically connected to the second impurity region via a second contact hole,
- wherein the gate electrode snakes between the first contact hole and the second contact hole.
An electronic device comprising a transistor, the transistor comprising:
- an active region including a first impurity region and a second impurity region;
- a plurality of gate electrodes adjacent to the active region;
- a first wiring electrically connected to the first impurity region via a first contact hole;
- and
- a second wiring electrically connected to the second impurity region via a second contact hole,
- wherein the plurality of gate electrodes snake between the first contact hole and the second contact hole.
An electronic device comprising a transistor, the transistor comprising:
- an active region including a first impurity region and a second impurity region;
- a gate electrode adjacent to the active region, wherein the gate electrode has at least two curvatures in a different direction with each other;
- a first wiring electrically connected to the first impurity region via a plurality of first contact holes;
- and
- a second wiring electrically connected to the second impurity region via a plurality of second contact holes,
- wherein the gate electrode snake between the plurality of first contact holes and the plurality of second contact holes.
An electronic device comprising a transistor, the transistor comprising:
- an active region including a first impurity region and a second impurity region;
- a plurality of gate electrodes adjacent to the active region;
- a first wiring electrically connected to the first impurity region via a plurality of first contact holes;
- and
- a second wiring electrically connected to the second impurity region via a plurality of second contact holes,
- wherein the plurality of gate electrodes snake between the plurality of first contact holes and the plurality of second contact holes.
Dependencies are inferred from the claim text.