Multi-level semiconductor device and method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorHan-Sin Lee
Life of this patent
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Abstract
A multi-level semiconductor device includes a first transistor on a semiconductor substrate, the first transistor including a first source/drain region, a semiconductor layer on the semiconductor substrate, a second transistor on the semiconductor layer, the second transistor including a second source/drain region in a first portion of the semiconductor layer, and a contact pattern extending from the first source/drain region and contacting a second portion of the semiconductor layer, wherein the second portion of the semiconductor layer has an impurity concentration that is greater than that of the second source/drain region.
Claims20
A multi-level semiconductor device, comprising:
- a first transistor on a semiconductor substrate, the first transistor including a first source/drain region;
- a semiconductor layer on the semiconductor substrate;
- a second transistor on the semiconductor layer, the second transistor including a second source/drain region in a first portion of the semiconductor layer;
- and
- a contact pattern extending from the first source/drain region and contacting a second portion of the semiconductor layer,
- wherein the second portion of the semiconductor layer has an impurity concentration that is greater than that of the second source/drain region.
A method of fabricating a multi-level semiconductor device, comprising:
- forming a first transistor on a semiconductor substrate, the first transistor including a first source/drain region;
- forming a semiconductor layer on the semiconductor substrate;
- forming a second transistor on the semiconductor layer, the second transistor including a second source/drain region in a first portion of the semiconductor layer;
- doping impurities in a second portion of the semiconductor layer to form a contact region having a higher impurity concentration than the second source/drain region;
- and
- forming a contact pattern that extends from the first source/drain region and contacts the contact region of the semiconductor layer.
Dependencies are inferred from the claim text.