Wafer level chip scale package system
AssigneeSTATS ChipPAC, Ltd.
InventorsKoo Hong Lee, Il Kwon Shim, Young Cheol Kim, Bongsuk Choi
Life of this patent
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Abstract
A wafer level chip scale package system is provided including placing a first integrated circuit over a semiconductor wafer having a second integrated circuit; connecting a second electrical interconnect between the first integrated circuit and the second integrated circuit; forming a stress relieving encapsulant on the outer perimeter of the second integrated circuit for covering the second electrical interconnect; and singulating a chip scale package, from the semiconductor wafer, through the stress relieving encapsulant and the semiconductor wafer.
Claims20
A wafer level chip scale package system comprising:
- placing a first integrated circuit over a semiconductor wafer having a second integrated circuit;
- connecting a second electrical interconnect between the first integrated circuit and the second integrated circuit;
- forming a stress relieving encapsulant on the outer perimeter of the second integrated circuit for covering the second electrical interconnect;
- and
- singulating a chip scale package, from the semiconductor wafer, through the stress relieving encapsulant and the semiconductor wafer.
A wafer level chip scale package system comprising:
- forming a base package having an first integrated circuit electrically connected to a package substrate including encapsulating the first integrated circuit, a first electrical interconnect, and a component side of the package substrate by a molded cap;
- placing the base package on a semiconductor wafer having a second integrated circuit including applying a pick and place machine for positioning the base package on an active surface of the second integrated circuit;
- connecting a second electrical interconnect electrically between the base package and the second integrated circuit including bonding a bond wire between the active surface of the second integrated circuit and a system side of the package substrate;
- forming a stress relieving encapsulant on the outer perimeter of the second integrated circuit for covering the second electrical interconnect includes molding an under-fill material;
- and
- singulating a chip scale package from the semiconductor wafer by sawing through the stress relieving encapsulant and the semiconductor wafer.
A wafer level chip scale package system comprising:
- a first integrated circuit placed over a semiconductor wafer having a second integrated circuit;
- a second electrical interconnect connected between the first integrated circuit and the second integrated circuit;
- a stress relieving encapsulant formed on the outer perimeter of the second integrated circuit for covering the second electrical interconnect;
- and
- a chip scale package singulated, from the semiconductor wafer, through the stress relieving encapsulant and the semiconductor wafer.
Dependencies are inferred from the claim text.