Heterojunction tunneling field effect transistors, and methods for fabricating the same

A semiconductor device, comprises:

• a semiconductor substrate,
• a tunneling field effect transistor (TFET) comprising spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region, wherein the source, drain, and channel regions of the TFET are located in the semiconductor substrate, wherein the drain region of the TFET comprises a first semiconductor material of a first conductivity type, wherein the source region of the TFET comprises a second, different semiconductor material of a second, different conductivity type, and wherein the gate stack of the TFET comprises at least a gate dielectric and a gate conductor;
• and
• a metal-oxide-semiconductor field effect transistor (MOSFET) adjacent to the TFET, wherein the MOSFET comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region, and wherein the source, drain, and channel regions of the MOSFET are located in the semiconductor substrate.

A method for forming a tunneling field effect transistor (TFET), comprising:

• providing a semiconductor substrate that comprises a first semiconductor material;
• forming a gate stack over the semiconductor substrate, wherein said gate stack comprises at least a gate dielectric and a gate conductor;
• doping the semiconductor substrate to form a first doped region and a second doped region in the semiconductor substrate, wherein the first and second doped regions both are doped with a first dopant species of a first conductivity type and are spaced apart from each other by the gate stack;
• selectively etching the second doped region to form a recess in the semiconductor substrate;
• selectively forming a semiconductor structure in the recess, wherein said semiconductor structure comprises a second, different semiconductor material of a second, different conductivity type,
• thereby forming a TFET, which comprises a drain region formed by the first doped region, a source region formed by the semiconductor structure, and a channel region that is located between and defined by the source and drain regions, with the gate stack located over the channel region.