Memory utilizing oxide-conductor nanolaminates

A method for forming a multistate memory array, comprising:

• forming a number of vertical pillars in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as floating gate transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate in the trenches along rows of pillars and separated from the channel region by a first gate oxide, and a control gate separated from the floating gate by a second gate oxide, wherein along columns of the pillars adjacent pillars include a floating gate transistor which operates as a multistate cell on one side of a trench and a floating gate transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench, and wherein forming the floating gate includes forming oxide-conductor nanolaminate layers including at least one metal conductor laminate layer;
• forming a number of bit lines coupled to the second source/drain region of each floating gate transistor along rows of the memory array;
• forming a number of word lines coupled to the control gate of each floating gate transistor along columns of the memory array;
• forming a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each floating gate transistor in column adjacent pillars couples to the sourceline in a shared trench such that a multistate cell floating gate transistor and a reference cell floating gate transistor share a common sourceline;
• and
• wherein the number of vertical pillars can be programmed to have a charge trapped in the floating gate by biasing a sourceline to a voltage higher than VDD, grounding a bitline, and selecting a control gate by a wordline address.

A method for forming a memory array, comprising:

• forming a plurality of memory cells, wherein forming at least one cell includes:
• forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate;
• forming a floating gate opposing the channel region and separated therefrom by a first gate oxide, wherein forming the floating gate includes forming oxide-conductor nanolaminate layers including at least one metal conductor laminate layer;
• and
• forming a control gate opposing the floating gate and separated therefrom by a second gate oxide.

A method for forming an electronic system, comprising:

• forming a memory array, wherein forming at least one memory cell in the array includes:
• forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate;
• forming a floating gate opposing the channel region and separated therefrom by a first gate oxide, wherein forming the floating gate includes forming oxide-conductor nanolaminate layers including at least one metal conductor laminate layer;
• forming a control gate opposing the floating gate and separated therefrom by a second gate oxide;
• forming a number of sense amplifiers to detect a signal from memory cells in the memory array;
• and
• coupling the memory array to a processor.