Methods for fabricating dram semiconductor devices including silicon epitaxial and metal silicide layers

A method for fabricating a DRAM semiconductor device comprising:

• forming a gate stack pattern on a cell region and a peripheral circuit region of a semiconductor substrate;
• forming a pair of n− source/drain regions in the cell region of the semiconductor substrate, a respective one of which extends to a respective opposing sidewall of the gate stack pattern of the cell region;
• forming a pair of n+ source/drain regions and a pair of p+ source/drain regions in the peripheral circuit region of the semiconductor substrate, a respective source/drain region of which extends to a respective sidewall of a respective gate stack in the gate stack pattern of the peripheral circuit region in the semiconductor substrate;
• forming a gate spacer on both opposing sidewalls of the gate stack pattern of the cell region and the peripheral circuit region;
• forming a silicon epitaxial layer on the n− source/drain regions, the n+ source/drain regions and the p+ source/drain regions on a lower portion of both sides of the gate spacer;
• forming a metal silicide layer on the silicon epitaxial layer of the cell region and the peripheral circuit region;
• forming a metal pad on the barrier layer of the cell region;
• and
• forming a metal plug on the barrier layer of the peripheral circuit region.