Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates

A method of forming a field effect transistor, comprising:

• forming masking material over semiconductive material of a substrate, the masking material comprising an outer insulative material layer and an inner insulative material layer, the outer insulative material layer being selectively etchable relative to the inner insulative material layer;
• forming a trench through the masking material and into the semiconductive material;
• forming gate dielectric material within the trench in the semiconductive material;
• depositing gate material within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material;
• recessing the gate material within the trench in the masking material;
• capping the recessed gate material within the trench within the masking material with insulative material of common composition to that of the inner insulative material layer;
• etching the outer insulative material layer selectively relative to the inner insulative material layer and to the capping insulative material received over the recessed gate material;
• after etching the outer insulative material layer, depositing insulative material of common composition to that of the inner insulative material layer;
• anisotropically etching the insulative material of common composition to that of the inner insulative material layer effective to form insulative sidewall spacers about the gate material;
• and
• forming source/drain regions.

A method of forming a field effect transistor gate, comprising:

• forming a silicon nitride-comprising masking material over semiconductive material of a substrate;
• forming a trench through the silicon nitride-comprising masking material and into the semiconductive material;
• removing silicon nitride of the masking material after forming the trench into the semiconductive material;
• prior to removing silicon nitride of the masking material, forming gate dielectric material within the trench in the semiconductive material;
• and
• depositing gate material within the trench in the semiconductive material over the gate dielectric material.

A method of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, comprising:

• forming masking material over semiconductive material of a substrate;
• forming array circuitry trenches through the masking material and into the semiconductive material;
• depositing array gate material within the array circuitry trenches in the masking material and within the array circuitry trenches in the semiconductive material;
• after depositing the array gate material, forming peripheral circuitry trenches through the masking material;
• and
• depositing peripheral circuitry gate material within the peripheral circuitry trenches within the masking material.

A method of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, comprising:

• forming masking material over semiconductive material of a substrate;
• forming array circuitry trenches through the masking material and into the semiconductive material;
• depositing array gate material within the array circuitry trenches in the masking material and within the array circuitry trenches in the semiconductive material;
• forming peripheral circuitry trenches through the array gate material and through the masking material;
• and
• depositing peripheral circuitry gate material within the peripheral circuitry trenches within the array gate material and within the masking material.

A method of forming field effect transistor gates, comprising:

• forming masking material over semiconductive material of a substrate, the substrate comprising a trench isolation region;
• in a common masking step, forming a first trench through the masking material and into the semiconductive material and forming a second grounded isolation gate trench through the masking material over the trench isolation region;
• and
• in a common deposition step, depositing gate material within the first trench and second trench.

A method of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates, comprising:

• forming masking material over semiconductive material of a substrate, the substrate comprising trench isolation regions;
• forming first trenches through the masking material and into the semiconductive material for the first gates;
• forming second grounded isolation gate trenches through the masking material over the trench isolation regions for the second grounded isolation gates;
• and
• depositing gate material within the first and second trenches.