Triple-well cmos devices with increased latch-up immunity and methods of fabricating same
AssigneeInternational Business Machines Corporation
InventorsDelbert Cecchi, Toshiharu Furukawa, Jack Mandelman
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Abstract
A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.
Claims15
A method, comprising:
- forming a P-type doped layer in a P-type silicon substrate, said P-type doped layer extending to a top surface of said substrate;
- forming an epitaxial layer on a top surface of said substrate to form a buried P-type doped layer from said P-type doped layer, a top surface of said buried P-type doped layer extending a first distance below a top surface of said epitaxial layer;
- forming an N-well and a P-well in said epitaxial layer, both said N-well and said P-well extending from a top surface of said epitaxial layer to a top surface of said buried P-type doped layer;
- forming a buried N-type doped layer in said P-well, a bottom surface of said buried N-type doped layer in contact with said top surface of said buried P-type doped layer, said buried N-type doped layer extending from said top surface of said buried P-type doped layer toward said top surface of said epitaxial layer a second distance, said second distance less than said first distance;
- forming a PFET in said N-well and forming an NFET in said P-well;
- forming a P-type contact in said P-well and forming an N-type contact in said N-well, both said P-type contact and said N-type contact extending from said top surface of said epitaxial layer into said epitaxial layer respective third and fourth distances, said third and fourth distances less than a fifth distance between said top surface of said buried N-type doped layer and said top surface of said epitaxial layer;
- and
- forming a gap in said buried N-type doped layer, said gap aligned under said P-type contact, said P-well contacting said top surface of said buried P-type doped layer in said gap.
A method of reducing latch-up in a CMOS device comprising:
- forming an N-well and an adjacent P-well in a silicon substrate;
- forming a PFET and a N-type contact in said N-well, forming an NFET and a P-type contact in said P-well;
- forming a buried N-type doped layer in said P-well, said CMOS device including a parasitic bipolar NPN transistor, an emitter of said parasitic bipolar NPN transistor comprising a source of said NFET, a base of said parasitic bipolar NPN transistor comprising a region of said P-well under said NFET, and a collector of said parasitic bipolar NPN transistor comprising said buried N-type doped layer and said N-well;
- and
- increasing a latch-up holding voltage of said CMOS device above a power supply voltage level supplied to said CMOS device by channeling holes around said bipolar NPN transistor parasitic transistor and into said P-well contact.
Dependencies are inferred from the claim text.