Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators

A method, comprising:

• forming a first source/drain region and a second source/drain region separated by a channel;
• forming a first gate adjacent the channel;
• forming a gate oxide separating the first gate from the channel;
• forming a second gate adjacent the first gate;
• and
• forming a graded, asymmetrical low tunnel barrier intergate insulator formed by multiple monolayer deposition separating the second gate from the first gate.

A method, comprising:

• forming a first source/drain region;
• forming a body region including a channel region on the first source/drain region;
• forming a second source/drain region on the body region;
• forming a floating gate adjacent the channel region and separated therefrom by a gate oxide;
• forming a control gate adjacent the floating gate;
• and
• forming a graded, asymmetrical low tunnel barrier intergate insulator separating the floating gate from the control gate, the graded, asymmetrical low tunnel barrier intergate insulator having a tunneling barrier of less than 2.0 eV and having a number of small compositional ranges such that gradients can be formed which produce different barrier heights at an interface with the floating gate and the control gate.

A method, comprising:

• forming a first source/drain region formed;
• forming a body region including a channel region on the first source/drain region;
• forming a second source/drain region on the body region;
• forming a floating gate opposing the channel region and separated therefrom by a gate oxide;
• forming a control gate opposing the floating gate;
• and
• forming an asymmetrical low tunnel barrier intergate insulator intermediate the floating gate and the control gate having a number of small compositional ranges to produce different barrier heights at an interface with the floating gate and control gate.

A method, comprising:

• forming a first source/drain region and a second source/drain region separated by a channel region;
• forming a polysilicon floating gate opposing the channel region and separated therefrom by a gate oxide, the floating gate including a horizontally oriented floating gate formed alongside of a body region;
• forming a first metal layer on the polysilicon floating gate;
• forming a metal oxide intergate insulator by monolayer deposition on the metal layer, the metal oxide intergate insulator including an asymmetrical metal oxide having a number of small compositional ranges such that gradients can be formed in an applied electric field to produce different barrier heights at an interface with the floating gate and control gate;
• forming a second metal layer on the metal oxide intergate insulator, the second metal layer having a different work function from the first metal layer;
• and
• forming a polysilicon control gate on the second metal layer.