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US 2007/0178634 A1Published application
Cmos semiconductor devices having dual work function metal gate stacks
OwnerHyung Suk Jung, Jong Ho Lee +3inventors
InventorsHyung Suk Jung, Jong Ho Lee, Sung Kee Han, Ju Youn Kim, Jung Min Park
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Abstract
CMOS semiconductor devices having dual work function metal gate structures that are formed using fabrication techniques that enable independent work function control for PMOS and NMOS device and which significantly reduce or otherwise eliminate impact on gate dielectric reliability.
Claims40
A semiconductor device, comprising:
- a semiconductor substrate having a dual-gate CMOS device formed on the semiconductor substrate, the dual-gate CMOS device comprising a PMOS device and an NMOS device,
- wherein the PMOS device has a first gate stack comprising:
- a gate insulating layer formed on the semiconductor substrate;
- a first conductive layer formed on the gate insulating layer;
- a second conductive layer formed on the first conductive layer;
- and
- a third conductive layer formed on the second conductive layer,
- wherein the NMOS device has a second gate stack comprising:
- a gate insulating layer formed on the semiconductor substrate;
- a first conductive layer formed on the gate insulating layer;
- and
- a second conductive layer formed on the first conductive layer, and
- wherein the second conductive layers of the first and second gate stacks are formed from different conductive materials.
10 more elements
A semiconductor device, comprising:
- a semiconductor substrate having a dual-gate CMOS device formed on a front-side of the semiconductor substrate, the dual-gate CMOS device comprising a PMOS device having a first MIPS gate stack, and an NMOS device having a second MIPS gate stack,
- wherein the first and second MIPS gate stacks each comprise:
- a gate insulating layer formed on the semiconductor substrate;
- a polysilicon electrode;
- and
- a metal inserted layer interposed between the gate insulating layer and the polysilicon electrode,
- wherein the metal inserted layer of the first MIPS gate stack comprises a stack of at least first, second and third metallic layers;
- and
- wherein the metal inserted layer of the second MIPS gate stack comprises at least a first metallic layer.
6 more elements
A method for fabricating a semiconductor device having a dual-gate CMOS device, the method comprising:
- defining an active region of a CMOS device on a semiconductor substrate, the active region comprising an NMOS device region and a PMOS device region;
- forming a gate insulating layer on the semiconductor substrate;
- forming a first conductive layer on the gate insulating layer;
- forming a second conductive layer on the first conductive layer;
- forming third conductive layer on the second conductive layer;
- performing an etch process to etch the third and second conductive layers down to the first conductive layer in the NMOS device region;
- and
- forming a first gate structure in the PMOS region and second gate structure in the NMOS region, wherein the first gate structure is stacked structure formed from the gate insulating layer and first and second conductive layers, and wherein the second gate structure is a stacked structure formed from the gate insulating layer and the first conductive layer.
5 more elements
Dependencies are inferred from the claim text.