Semiconductor Arrangement
AssigneeInfineon Technologies AG
InventorsNikolaus Bott, Oliver Haeberlen, Manfred Kotek, Joost Larik, Josef Maerz, Ralf Otremba
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Abstract
The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.
Claims19
A method for fabricating a semiconductor arrangement comprising:
- providing a lower semiconductor component with a topmost, patterned metallization;
- depositing a passivation layer;
- patterning the passivation layer by means of photolithography and a first etching step;
- depositing a polyimide layer;
- opening the polyimide layer in a contact pad region by means of photolithography;
- fixing an upper semiconductor component on the passivation layer;
- and
- sheathing the semiconductor arrangement with a molding composition, wherein after patterning, the passivation layer essentially remains only in the region below the upper semiconductor component.
A method for fabricating a semiconductor arrangement comprising:
- providing a lower semiconductor component with a topmost, patterned metallization;
- depositing a first passivation layer having a first thickness;
- depositing a second passivation layer having a second thickness greater than the first thickness;
- patterning the second passivation layer by means of photolithography and a first etching step;
- depositing a polyimide layer;
- opening the polyimide layer and the first passivation layer in a contact pad region by means of photolithography and a second etching step;
- fixing an upper semiconductor component on the passivation layer;
- and
- sheathing the semiconductor arrangement with a molding composition, wherein after patterning, the second passivation layer essentially remains only in the region directly below the upper semiconductor component.
A method for fabricating a semiconductor arrangement comprising:
- providing a lower semiconductor component;
- depositing a metal layer;
- depositing a first passivation layer having a first thickness;
- patterning the first passivation layer by means of photolithography and a first etching step;
- heat treatment in a forming gas atmosphere;
- patterning the metal layer by means of photolithography and a second etching step;
- depositing a second passivation layer having a second thickness;
- depositing a polyimide layer;
- opening the polyimide layer and the second passivation layer in a contact pad region by means of photolithography and a third etching step;
- fixing an upper semiconductor component on the passivation layer;
- sheathing the semiconductor arrangement with a molding composition, wherein after patterning, the first passivation layer essentially remains only in the region below the upper semiconductor component.
A method for fabricating a semiconductor arrangement comprising a lower and at least one upper semiconductor component in a housing comprising:
- providing a lower semiconductor component;
- depositing a metal layer;
- depositing a passivation layer;
- patterning the passivation layer by means of photolithography and a first etching step;
- heat treatment in a forming gas atmosphere;
- patterning the metal layer by means of photolithography and a second etching step;
- fixing the upper semiconductor component on the passivation layer;
- producing an electrical connection between the lower and at least one upper semiconductor component;
- depositing an adhesion promoting layer;
- sheathing the semiconductor arrangement with a molding composition, wherein after patterning, the passivation layer essentially remains only in the region below the upper semiconductor component.
Dependencies are inferred from the claim text.