Thin film transistor array panel and method of manufacturing the same

A method of manufacturing a thin film transistor (TFT) array panel, the method comprising:

• forming gate lines on a substrate;
• forming a gate insulation layer, a semiconductor layer, and an ohmic contact layer on the gate lines;
• forming a conductive layer on the ohmic contact layer;
• forming a first photosensitive layer pattern on the conductive layer;
• etching the conductive layer using the first photosensitive layer pattern as an etching mask;
• etching the ohmic contact layer and the semiconductor layer by a fluorine-containing gas, a chloride-containing gas, and an oxygen (O2) gas using the first photosensitive layer pattern as an etching mask, wherein the flow ratio between the fluorine-containing gas and the oxygen gas is in the range of about 4:1 to about 1:1;
• removing the first photosensitive layer pattern to a predetermined thickness to form a second photosensitive layer pattern;
• and
• etching the conductive layer using the second photosensitive layer pattern as an etching mask to expose a part of the ohmic contact layer.

A thin film transistor (TFT) array panel, comprising:

• a substrate;
• gate lines formed on the substrate;
• a gate insulation layer formed on the gate lines;
• a semiconductor layer formed on the gate insulation layer;
• data lines formed on the semiconductor layer and including source electrodes;
• drain electrodes formed on the semiconductor layer to face the source electrodes;
• and
• pixel electrodes connected to the drain electrodes,
• wherein the semiconductor layer has substantially the same planar shape as the data lines and the drain electrodes, and
• the length of the semiconductor layer side projections is no more than 1.5 μm.