Receiver and method for synchronizing and aligning serial streams
AssigneeATI Technologies, Inc.
InventorHaran Thanigasalam
Life of this patent
Estimating the term…
Abstract
A receiver for receiving a stream of symbols clocked at a first rate, and providing the symbols at a second clock rate uses two buffers. Incoming symbols are written to a first dual clock buffer at the first rate, and read from the first and second buffer, at the second rate. Underflow of the first buffer is signaled to the second buffer, thereby avoiding the need to insert defined clock compensation symbols at the second rate. Symbols received at the second buffer while underflow is signaled may be ignored. Conveniently, the second buffer may also be used to align symbol data across multiple symbol streams using periodic alignment symbols. An exemplary embodiment conforms to the PCI Express standard.
Claims36
A receiver for providing symbols at a second clock rate from an incoming stream of symbols clocked at a first clock rate, comprising:
- a first buffer for storing symbols in said incoming stream at said first clock rate;
- a first buffer control circuit for providing symbols stored in said first buffer and placeholder symbols at said second clock rate, and an indicator of whether a provided symbol is a placeholder symbol, wherein said placeholder symbols are provided when insufficient symbols are stored within said first buffer;
- a second buffer for storing corresponding symbols, said corresponding symbols corresponding to said symbols provided from said first buffer;
- a second buffer control circuit for receiving said indicator and inhibiting placeholder symbols from entering said second buffer, and providing said corresponding symbols from said second buffer at said second clock rate.
A method of synchronizing an incoming stream of symbols clocked at a first clock rate, to a second clock rate, said method comprising:
- receiving said stream in a first buffer at said first clock rate;
- providing symbols stored in said first buffer and placeholder symbols at said second clock rate, and an indicator of whether a provided symbol is a placeholder symbol, wherein said placeholder symbols are provided when insufficient symbols are stored within said first buffer;
- storing symbols corresponding to said symbols provided from said first buffer, in a second buffer and inhibiting placeholder symbols from being stored in said second buffer;
- and
- providing said corresponding symbols stored in said second buffer at said second clock rate.
A circuit for removing skew among a plurality of symbol streams each symbol stream including periodic alignment symbols, said circuit comprising:
- a plurality of buffers, each used to buffer symbols within one of said symbol streams;
- a plurality of read pointers, each identifying a location of one of said buffers from which data is to be read;
- control logic to detect placeholder symbols in each of said symbol streams, and prevent said placeholder symbols from being stored in an associated one of said buffers;
- and
- alignment logic, for aligning said read pointers to concurrently point to said periodic alignment symbols in each of said buffers.
A method of removing skew among a plurality of symbol streams each symbol stream including periodic alignment symbols, said method comprising:
- buffering symbols within each of said symbol streams in a plurality of buffers;
- detecting placeholder symbols in each of said symbol streams, and preventing said placeholder symbols from being stored in an associated one of said buffers;
- identifying a location of said buffers from which data is to be read using a plurality of read pointers each associated with one of said buffers;
- and
- aligning said read pointers to concurrently point to said periodic alignment symbols in each of said buffers in response to an alignment condition being met.
Dependencies are inferred from the claim text.